Epson S1D13708 Benutzerhandbuch
Epson Research and Development
Page 103
Vancouver Design Center
Hardware Functional Specification
S1D13708
Issue Date: 02/03/07
X39A-A-001-02
1.
Ts
= pixel clock period
2.
t1typ
= (REG[12h] bits 6-0) +1) x 8
3.
t3typ
= Selected from 7, 9, 12 or 16 Ts in REG[D0h] bits 1-0
4.
t4typ
= Selected from 7, 9, 12 or 16 Ts in REG[D0h] bits 4-3
5.
t5typ
= (REG[17h] bits 1-0, REG[16h] bits 7-0) + 3
6.
t9typ
= ((REG[14h] bits 6-0) +1) x 8
7.
t10typ = Selected from 40, 52, 68 or 90 Ts in REG[D1h] bits 1-0
8.
t11typ = Selected from 20, 40, 80, 120, 150, 190, 240 or 270 Ts in REG[D1h] bits 5-3
Table 6-36: TFT Type 2 Horizontal Timing
Symbol
Parameter
Min
Typ
Max
Units
t1
Horizontal total period
1
note 2
1024
Ts (note 1)
t2
FPLINE pulse width
5
Ts
t3
GPIO0 rising edge to FPLINE rising edge
7
note 3
16
Ts
t4
FPLINE rising edge to GPIO0 falling edge
7
note 4
16
Ts
t5
FPLINE rising edge to GPIO3 rising edge
note 5
Ts
t6
GPIO3 pulse width
1
Ts
t7
Data setup time
0.5
Ts
t8
Data hold time
0.5
Ts
t9
Horizontal display period
8
note 6
1024
Ts
t10
FPLINE rising edge to GPIO1 rising edge
40
note 7
90
Ts
t11
GPIO1 pulse width
20
note 8
270
Ts
t12
FPLINE rising edge to GPIO2 toggle position
10
Ts