Epson S1D13708 Benutzerhandbuch
Epson Research and Development
Page 143
Vancouver Design Center
Hardware Functional Specification
S1D13708
Issue Date: 02/03/07
X39A-A-001-02
8.3.7 Miscellaneous Registers
bit 7
Vertical Non-Display Period Status
This is a read-only status bit.
When this bit = 0, the LCD panel output is in a Vertical Display Period.
When this bit = 1, the LCD panel output is in a Vertical Non-Display Period.
This is a read-only status bit.
When this bit = 0, the LCD panel output is in a Vertical Display Period.
When this bit = 1, the LCD panel output is in a Vertical Non-Display Period.
bit 3
Memory Controller Power Save Status
This read-only status bit indicates the power save state of the memory controller.
When this bit = 0, the memory controller is powered up.
When this bit = 1, the memory controller is powered down and the MCLK source can be
turned off.
This read-only status bit indicates the power save state of the memory controller.
When this bit = 0, the memory controller is powered up.
When this bit = 1, the memory controller is powered down and the MCLK source can be
turned off.
Note
Memory writes are possible during power save mode because the S1D13708 dynamical-
ly enables the memory controller for display buffer writes.
ly enables the memory controller for display buffer writes.
bit 0
Power Save Mode Enable
When this bit = 1, the software initiated power save mode is enabled.
When this bit = 0, the software initiated power save mode is disabled.
At reset, this bit is set to 1. For a summary of Power Save Mode, see Section 18, “Power
Save Mode” on page 215.
When this bit = 1, the software initiated power save mode is enabled.
When this bit = 0, the software initiated power save mode is disabled.
At reset, this bit is set to 1. For a summary of Power Save Mode, see Section 18, “Power
Save Mode” on page 215.
Note
Memory writes are possible during power save mode because the S1D13708 dynamical-
ly enables the memory controller for display buffer writes.
ly enables the memory controller for display buffer writes.
bit 0
Reserved.
This bit must be set to 0.
This bit must be set to 0.
Power Save Configuration Register
REG[A0h]
REG[A0h]
Read/Write
Vertical Non-
Display
Period Status
(RO)
n/a
Memory
Controller
Power Save
Status (RO)
n/a
Power Save
Mode Enable
7
6
5
4
3
2
1
0
Reserved
REG[A1h]
REG[A1h]
Read/Write
n/a
Reserved
7
6
5
4
3
2
1
0