Epson S1D13708 Benutzerhandbuch
Page 196
Epson Research and Development
Vancouver Design Center
S1D13708
Hardware Functional Specification
X39A-A-001-02
Issue Date: 02/03/07
The following shows an example of a “memory write” for Mode 68 when the Memory
Access Select bit is enabled (REG[C6h] bit 0 = 1).
Access Select bit is enabled (REG[C6h] bit 0 = 1).
Figure 15-5 Sample timing of “register write” for Mode 68 when Memory Access Select Enabled
1. write register number of Memory Access Start register (REG[C4h]) (command write).
Note
No “data write” is required after a command write to the Memory Access Start register
(REG[C4h]). This step configures the S1D13708 for burst memory access beginning
with the next data write.
(REG[C4h]). This step configures the S1D13708 for burst memory access beginning
with the next data write.
2. write Memory data (data write).
If the Memory Access Select bit (REG[C6h] bit 0 = 1), memory accesses are word ac-
cesses even if EBU is high (EBU is ignored and EBL is used to write both the upper
and lower bytes). The big/little endian setting is used to determine the data arrange-
ment for word accesses only.
cesses even if EBU is high (EBU is ignored and EBL is used to write both the upper
and lower bytes). The big/little endian setting is used to determine the data arrange-
ment for word accesses only.
A0
CS#
EBL
R/W#
EBU
D[7:0]
D[15:8]
Little endian
DATA2
DATA0
DATA8
DATA12
command write
MemoryAccessStart
data write
data write
data write
data write
word access
DATA9
DATA n+1
DATA n
Big Endian
D[7:0]
D[15:8]
data write
data write
data write
DATA4
DATA6
DATA10
DATA11
DATA n
DATA n+1
Little Endian
Data arrangement
word access
DATA1
DATA3
DATA5
DATA7
DATA13
word access
word access
word access
word access
word access
Address +2
(word)
Address +2
(word)
Address +2
(word)
Address +2
(word)
Address +2
(word)
Address +2
(word)
1
2
2
2
2
2
2
2
STEP