Epson S1D13708 Benutzerhandbuch

Page 3

Vancouver Design Center

Power Consumption

S1D13708

Issue Date: 01/11/25 

X39A-G-006-01

The S1D13708 power consumption can be affected by many system design variables. 
Some of the variables to consider are:

• Input Clock Frequency (CLKI/CLKI2/XTAL): CLKI/CLKI2/XTAL frequency 

determines the LCD frame-rate, CPU performance to memory, and other functions – the 
higher the input clock frequency will result in higher power consumption.

• CPU interface: the S1D13708 current consumption depends on the BCLK frequency, 

data width, number of toggling pins, and other factors – using higher BCLK gives 
higher CPU performance but results in higher power consumption.

• V

 Voltage Level: the voltage level affects power consumption – the higher the 

voltage, the higher the power consumption.

• Display Mode: the resolution and color depth affect power consumption – the higher 

the
resolution/color depth, the higher the power consumption.

• Internal CLK Divide: internal registers allow the input clock to be divided before 

going to the internal logic blocks – the higher the divide, the lower the power consump-
tion.

There is a power save mode in the S1D13708 where the power consumption is affected by 
various system design variables.

• Clock States During The Power Save Mode: disabling the clock oscillation during 

power save mode has substantial power savings.

All unused input pins are tied to ground or as specified in the Hardware Functional Speci-
fication, document number X39A-A-001-xx.