Epson S1D13708 Benutzerhandbuch
Page 12
Epson Research and Development
Vancouver Design Center
S1D13708
Interfacing to the NEC VR4102 / VR4111 Microprocessors
X39A-G-007-01
Issue Date: 01/11/05
4 VR4102/VR4111 to S1D13708 Interface
4.1 Hardware Description
The NEC VR4102/VR4111 microprocessor is specifically designed to support an external
LCD controller by providing the internal address decoding and control signals necessary.
By using the Generic # 2 Host Bus Interface, no glue logic is required to interface the
S1D13708 and the NEC VR4102/VR4111.
LCD controller by providing the internal address decoding and control signals necessary.
By using the Generic # 2 Host Bus Interface, no glue logic is required to interface the
S1D13708 and the NEC VR4102/VR4111.
A pull-up resistor is attached to WAIT# to speed its rise time when terminating a cycle.
BS# (bus start) and RD/WR# are not used by the Generic #2 Host Bus Interface and must
be tied high (connected to IO V
be tied high (connected to IO V
DD
).
The following diagram shows a typical implementation of the VR4102/VR4111 to
S1D13708 interface.
S1D13708 interface.
Figure 4-1: Typical Implementation of VR4102/VR4111 to S1D13708 Interface
WE1#
WE0#
DB[15:0]
WAIT#
RD#
CLKI
S1D13708
CS#
RESET#
AB[16:0]
SHB#
WR#
DAT[15:0]
LCDCS#
RD#
BUSCLK
LCDRDY
ADD[16:0]
NEC VR4102/VR4111
Pull-up
BS#
RD/WR#
System RESET
Note:
When connecting the S1D13708 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13708 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
When connecting the S1D13708 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13708 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
IO V
DD
M/R#
ADD17
IO V
DD