Epson S1D13708 Benutzerhandbuch
Page 34
Epson Research and Development
Vancouver Design Center
S1D13708
Hardware Functional Specification
X39A-A-001-02
Issue Date: 02/03/07
4.3.2 LCD Interface
Table 4-4: LCD Interface Pin Descriptions
Pin Name
Type
PFBGA
Pin #
Cell
IO
Voltage
RESET#
State
Description
FPDAT[17:0]
O
A4,A5,
A6,A7,
A8,B4,
B6,B7,
A6,A7,
A8,B4,
B6,B7,
B8,C4,
C5,C6,
C8,C9,
D5,D6,
C5,C6,
C8,C9,
D5,D6,
D7,D8
PBCC8
IOVDD
0
Panel Data bits 17-0.
FPFRAME
O
J8
PBCC8
IOVDD
0
This output pin has multiple functions.
• Frame Pulse
• SPS for Sharp HR-TFT
• DY for Epson D-TFD
• STV for TFT Type 2
• STV for Type 3
for
summary.
FPLINE
O
L9
PBCC8
IOVDD
0
This output pin has multiple functions.
• Line Pulse
• LP for Sharp HR-TFT
• LP for Epson D-TFD
• STB for TFT Type 2
• LP for Type 3
for
summary.
FPSHIFT
O
G10
PBCC8
IOVDD
0
This output pin has multiple functions.
• Shift Clock
• CLK for Sharp HR-TFT
• XSCL for Epson D-TFD
• CLK for TFT Type 2
• CPH for Type 3
for
summary.
DRDY
O
H11
POC8
IOVDD
0
This output pin has multiple functions.
• Display enable (DRDY) for TFT panels
• 2nd shift clock (FPSHIFT2) for passive LCD with Format 1
interface
• GCP for Epson D-TFD
• INV for TFT Type 2
• INV for TFT Type 3
• LCD backplane bias signal (MOD) for all other LCD panels
for
summary.