Epson S1D13708 Benutzerhandbuch
Page 12
Epson Research and Development
Vancouver Design Center
S1D13708
Interfacing to the NEC VR4181A™ Microprocessor
X39A-G-008-01
Issue Date: 01/11/05
4 VR4181A to S1D13708 Interface
4.1 Hardware Description
The NEC VR4181A microprocessor is specifically designed to support an external LCD
controller by providing the internal address decoding and control signals necessary. By
using the Generic # 2 Host Bus Interface, no glue logic is required to interface the
S1D13708 to the NEC VR4181A.
controller by providing the internal address decoding and control signals necessary. By
using the Generic # 2 Host Bus Interface, no glue logic is required to interface the
S1D13708 to the NEC VR4181A.
A pull-up resistor is attached to WAIT# to speed up its rise time when terminating a cycle.
#MEMCS16 of the NEC VR4181A is connected to #LCDCS to signal that the S1D13708
is capable of 16-bit transfers.
is capable of 16-bit transfers.
BS# (bus start) and RD/WR# are not used by the Generic #2 Host Bus Interface and must
be tied high (connected to IO V
be tied high (connected to IO V
DD
).
The diagram below shows a typical implementation of the VR4181A to S1D13708
interface.
interface.
Figure 4-1: Typical Implementation of VR4181A to S1D13708 Interface
WE1#
WE0#
DB[15:0]
WAIT#
RD#
CLKI
S1D13708
CS#
RESET#
AB[16:0]
#UBE
#MEMWR
D[15:0]
#LCDCS
#MEMRD
IORDY
A[16:0]
NEC VR4181A
Pull-up
BS#
RD/WR#
System RESET
#MEMCS16
Note:
When connecting the S1D13708 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13708 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
When connecting the S1D13708 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13708 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
M/R#
A17
IO V
DD
SYSCLK
IO V
DD