Epson S1D13708 Benutzerhandbuch
Epson Research and Development
Page 13
Vancouver Design Center
Interfacing to the Motorola MPC821 Microprocessor
S1D13708
Issue Date: 01/11/06
X39A-G-009-01
3 S1D13708 Host Bus Interface
The S1D13708 directly supports multiple processors. The S1D13708 implements a 16-bit
Generic #1 Host Bus Interface which is most suitable for direct connection to the Motorola
MPC821 microprocessor. Generic #1 supports a Chip Select and an individual Read
Enable/Write Enable for each byte.
Generic #1 Host Bus Interface which is most suitable for direct connection to the Motorola
MPC821 microprocessor. Generic #1 supports a Chip Select and an individual Read
Enable/Write Enable for each byte.
The Generic #1 Host Bus Interface is selected by the S1D13708 on the rising edge of
RESET#. After RESET# is released, the bus interface signals assume their selected config-
uration. For details on the S1D13708 configuration, see Section 4.3, “S1D13708 Hardware
Configuration” on page 18.
RESET#. After RESET# is released, the bus interface signals assume their selected config-
uration. For details on the S1D13708 configuration, see Section 4.3, “S1D13708 Hardware
Configuration” on page 18.
3.1 Host Bus Interface Pin Mapping
The following table shows the functions of each Host Bus Interface signal.
Note
The Motorola MPC821 chip select module only handles 16-bit read cycles. As the
S1D13708 uses the chip select module to generate CS#, only 16-bit read cycles are pos-
sible and both the high and low byte enables can be driven by the MPC821 signal OE.
S1D13708 uses the chip select module to generate CS#, only 16-bit read cycles are pos-
sible and both the high and low byte enables can be driven by the MPC821 signal OE.
Table 3-1: Host Bus Interface Pin Mapping
S1D13708
Pin Names
Motorola MPC821
AB[16:0]
A[15:31]
DB[15:0]
D[0:15]
WE1#
WE0
CS#
CS4
M/R#
A14
CLKI
SYSCLK
BS#
Connect to IO V
DD
RD/WR#
OE (see note)
RD#
OE (see note)
WE0#
WE1
WAIT#
TA
RESET#
System RESET