Epson S1D13708 Benutzerhandbuch
Epson Research and Development
Page 11
Vancouver Design Center
Interfacing to the Intel StrongARM SA-1110 Microprocessor
S1D13708
Issue Date: 01/11/25
X39A-G-019-01
3 S1D13708 Host Bus Interface
The S1D13708 directly supports multiple processors. The S1D13708 implements a 16-bit
Generic #2 Host Bus Interface which is most suitable for direct connection to the
SA-1110.
Generic #2 Host Bus Interface which is most suitable for direct connection to the
SA-1110.
The Generic #2 Host Bus Interface is selected by the S1D13708 on the rising edge of
RESET#. After releasing reset the bus interface signals assume their selected configuration.
For details on S1D13708 configuration, see Section 4.2, “S1D13708 Hardware Configu-
ration” on page 14.
RESET#. After releasing reset the bus interface signals assume their selected configuration.
For details on S1D13708 configuration, see Section 4.2, “S1D13708 Hardware Configu-
ration” on page 14.
The S1D13708 clock (CLKI) is taken from the system host bus. The system clock source
will drive all required internal clocks. If they are not used, the CLKI2 and XTAL inputs
should be tied to ground.
will drive all required internal clocks. If they are not used, the CLKI2 and XTAL inputs
should be tied to ground.
3.1 Host Bus Interface Pin Mapping
The following table shows the functions of each Host Bus Interface signal.
Table 3-1: Host Bus Interface Pin Mapping
S1D13708 Pin Name
SA-1110
AB[16:0]
A[16:0]
DB[15:0]
D[15:0]
WE1#
nCAS1
M/R#
A17
CS#
nCS4
CLKI
SDCLK2
BS#
V
DD
RD/WR#
V
DD
RD#
nOE
WE0#
nWE
WAIT#
RDY
RESET#
system RESET