Epson S1D13708 Benutzerhandbuch
Epson Research and Development
Page 67
Vancouver Design Center
Hardware Functional Specification
S1D13708
Issue Date: 02/03/07
X39A-A-001-02
6.3.2 Passive/TFT Power-Off Sequence
Figure 6-14 Passive/TFT Power-Off Sequence Timing
1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel
connected.
Table 6-17: Passive/TFT Power-Off Sequence Timing
Symbol
Parameter
Min
Max
Units
t1
LCD bias deactivated to LCD signals inactive
Note 1
Note 1
t2
Power Save Mode enabled to LCD signals low
0
20
ns
LCD Signals***
GPO0*
t1
*It is recommended to use the general purpose output pin GPO0 to control the LCD bias power.
**The LCD power-off sequence is activated by programming the Power Save Mode Enable bit (REG[A0h] bit 0) to 1.
***LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, and DRDY.
**The LCD power-off sequence is activated by programming the Power Save Mode Enable bit (REG[A0h] bit 0) to 1.
***LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, and DRDY.
t2
Power Save
(REG[A0h] bit 0)
Mode Enable**