Epson S1D13708 Benutzerhandbuch

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Epson Research and Development

Vancouver Design Center

S1D13708

Hardware Functional Specification

X39A-A-001-02

Issue Date: 02/03/07

6.4.4 Single Color 4-Bit Panel Timing

Figure 6-21 Single Color 4-Bit Panel Timing

VDP

= Vertical Display Period
= (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) + 1 Lines

VNDP

= Vertical Non-Display Period
= VT - VDP
= (REG[19h] bits 1:0, REG[18h] bits 7:0) - (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) Lines

HDP

= Horizontal Display Period
= ((REG[14h] bits 6:0) + 1) x 8Ts

HNDP

= Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6:0) + 1) x 8Ts) - (((REG[14h] bits 6:0) + 1) x 8Ts)

FPLINE

FPFRAME

FPLINE

DRDY (MOD)

FPSHIFT

VDP

LINE1

LINE2

LINE3

LINE4

LINE239 LINE240

LINE1

LINE2

VNDP

1-R1

1-G1

1-B1

1-R2

1-G2

1-B2

1-R3

1-G3

1-B3

1-R4

1-G4

1-B4

1-B319

1-R320

1-G320

1-B320

HDP

HNDP

FPDAT[7:4]

FPDAT4

FPDAT5

FPDAT6

FPDAT7

Invalid

- Diagram drawn with 2 FPLINE vertical blank period
- Example timing for a 320x240 panel

Notes:

- Ts = Pixel clock period (PCLK)

- FPSHIFT uses extended low states in order to process 8 pixels in 6 FPSHIFT clocks

.5Ts

2.5Ts

.5Ts