Xilinx XAPP721 Benutzerhandbuch
Write Datapath
R
Write Datapath
The write datapath uses the built-in OSERDES available in every Virtex-4 I/O. The OSERDES
transmits the data (DQ) and strobe (DQS) signals. The memory specification requires DQS to
be transmitted center-aligned with DQ. The strobe (DQS) forwarded to the memory is
180 degrees out of phase with CLKfast_0. Therefore, the write data transmitted using
OSERDES must be clocked by CLKfast_90 and CLKdiv_90 as shown in
transmits the data (DQ) and strobe (DQS) signals. The memory specification requires DQS to
be transmitted center-aligned with DQ. The strobe (DQS) forwarded to the memory is
180 degrees out of phase with CLKfast_0. Therefore, the write data transmitted using
OSERDES must be clocked by CLKfast_90 and CLKdiv_90 as shown in
Figure 3
. The timing
diagram for write DQS and DQ is shown in
Figure 4
.
Figure 1: Clocking Scheme for the High-Performance Memory Interface Design
Figure 2: Command and Control Timing
DCM
CLKfast Input
CLKfast_0
CLKIN
RST
CLKFB
CLK0
CLK90
LOCKED
x702_04_051105
System Reset*
*
*
PMCD#1
CLKA
RST
CLKFB
CLKA1
CLKA1D2
PMCD#2
CLKA
CLKB
RST
CLKFB
CLKA1
CLKA1D2
CLKdiv_0
CLKfast_90
CLKdiv_90
CLKdiv_0
CLKfast_0
Memory Device
Clock
Clock
Command
WRITE
IDLE
Control (CS_L)
X721_02_080205
56
Memory Interfaces Solution Guide
March 2006