Intel 815 Benutzerhandbuch
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
326
16.2.5. ISR—Interrupt Status Register
Address Offset:
020ACh
Default Value:
0100h (probably still not quite correct value)
Access: Read
Only
Size: 16
bits
This register contains the non-persistent value of the signals causing each interrupt. These bits are not
masked by the Interrupt Mask Register. The user interrupt and the breakpoint interrupt last for one clock
pulse. The corresponding bits in this register will serve no practical purpose due to the short duration of
the signal.
masked by the Interrupt Mask Register. The user interrupt and the breakpoint interrupt last for one clock
pulse. The corresponding bits in this register will serve no practical purpose due to the short duration of
the signal.
15 14
13 12
11
10
9
8
HW
Detect
Error
Master
Reserved Sync
Status
Toggle
Pri Dply
Flip
Pending
Reserved Overlay
0
Flip
Pending
Reserved
7 6 5 4 3 2 1 0
Pri Dply
VBLANK.
Pri Dply
Event
Reserved Reserved Reserved Reserved User
Defined
Interrupt
Breakpoint
Bit Description
15:0
Interrupt Status. See Table 17.
1 = Signal caused interrupt.