Benutzerhandbuch für Intel 815

Intel

Benutzerhandbuch (English)

Benutzerhandbuch

Inhaltsverzeichnis

Contents
3
Figures
11
Tables
12
Revision History
13
Introduction
15
- Terminology
  15
- Reference Documents
  16
Intel® 815 Chipset Overview
17
- I/O Controller Hub
  18
- Intel® 82815 Chipset GMCH Overview
  18
- Three PCI Devices on GMCH
  22
  - Multi-Mode Capability Requirements
    23
System Address Map
29
- Memory and I/O Space Registers
  30
- GC Register Memory Address Map
  32
- VGA and Extended VGA Register Map
  36
  - VGA and Extended VGA I/O and Memory Register Map
    37
- Indirect VGA and Extended VGA Register Indices
  38
  - Graphics Address Translation
    41
  - Memory Buffers for GC’s Instruction Interface
    42
Graphics Translation Table (GTT) Range Definition
43
Basic Initialization Procedures
45
- Initialization Sequence
  45
- Hardware Detection (Probe)
  45
- Frame Buffer Initialization
  46
- Hardware Register Initialization
  47
- Hardware State
  47
- Saving the Hardware State
  48
- Restoring the Hardware State
  49
Blt Engine Programming
53
- BLT Engine Programming Considerations
  53
  - When the Source and Destination Locations Overlap
    53
- Basic Graphics Data Considerations
  57
  - Contiguous vs. Discontinuous Graphics Data
    57
  - Source Data
    58
  - Monochrome Source Data
    59
  - Pattern Data
    60
  - Destination Data
    62
- BLT Programming Examples
  63
  - Pattern Fill -- A Very Simple BLT
    63
  - Drawing Characters Using a Font Stored in System Memory
    66
Initialization Registers
69
- Standard VGA Registers
  69
- SMRAM Registers
  69
  - SMRAM—System Management RAM Control Register (Device 0)
    69
- Display, I/O, GPIO, Clock, LCD, and Pixel Pipeline Registers
  72
- 2D Graphics Controller Registers (3CEh / 3CFh)
  73
- 2D CRT Controller Registers (3B4h/3D4h/3B5h/3D5h)
  73
- Initialization Values for VGA Registers
  74
Frame Buffer Access
77
VGA and Extended VGA Registers
79
- General Control & Status Registers
  79
  - ST00(Input Status 0
    80
  - ST01(Input Status 1
    81
  - FCR(Feature Control
    82
  - MSR(Miscellaneous Output
    83
- Sequencer Registers
  84
- Graphics Controller Registers
  90
- Attribute Controller Registers
  101
- VGA Color Palette Registers
  106
- CRT Controller Register
  109
Programming Interface
141
- Reserved Bits and Software Compatibility
  141
- Overview
  141
- GC Register Programming
  142
- GC Instruction Streams
  142
  - Instruction Use
    142
  - Instruction Transport Overview
    142
  - Instruction Parser
    143
  - Ring Buffers (RB)
    144
    - Ring Buffer Registers
      144
    - Ring Buffer Initialization
      145
    - Ring Buffer Use
      145
  - Batch Buffers
    146
  - Instruction Arbitration
    147
    - Arbitration Rationale
      147
    - Wait Instructions
      147
    - Instruction Arbitration Points
      148
    - Instruction Arbitration Rules
      148
    - Batch Buffer Protected Mode
      148
- Instruction Format
  149
  - Instruction Parser Instructions
    149
  - 2D Instructions
    149
  - 3D Instructions
    150
Instruction Parser Instructions
153
- Introduction
  153
- Instruction Descriptions
  153
  - GFXCMDPARSER_NOP_IDENTIFICATION
    153
  - GFXCMDPARSER_BREAKPOINT_INTERRUPT
    154
  - GFXCMDPARSER_USER_INTERRUPT
    154
  - GFXCMDPARSER_WAIT_FOR_EVENT
    155
  - GFXCMDPARSER_FLUSH
    156
  - GFXCMDPARSER_CONTEXT _SEL
    156
  - GFXCMDPARSER _DEST_BUFFER_INFO
    157
  - GFXCMDPARSER _FRONT_BUFFER_INFO
    158
  - GFXCMDPARSER _Z_BUFFER_INFO
    159
  - GFXCMDPARSER_REPORT_HEAD
    159
  - GFXCMDPARSER_ARB_ON_OFF
    160
  - GFXCMDPARSER_OVERLAY_FLIP
    160
2D Instructions
163
- BLTs To and From Cacheable Memory
  163
- BLT Engine Instructions
  163
- BLT Engine Instruction Definitions
  184
Rendering Engine Instructions
205
- GFXPRIMITIVE
  205
  - Axis Aligned Rectangles
    205
  - Primitive Winding Order
    205
  - Position Mask
    206
  - Bias
    206
  - Primitive Rendering Instruction Format
    206
  - Variable Length Vertex Formats for Rendering Instructions
    207
  - GFXVERTEX
    208
- GFXRENDERSTATE_VERTEX_FORMAT
  209
- GFXBLOCK
  210
  - Motion Vector Format
    213
- Non-pipelined State Variables
  213
- GFXRENDERSTATE_MAP_TEXELS
  214
- GFXRENDERSTATE_MAP_COORD_SETS
  215
- GFXRENDERSTATE_MAP_INFO
  217
- GFXRENDERSTATE_MAP_FILTER
  222
- GFXRENDERSTATE_MAP_LOD_LIMITS
  224
- GFXRENDERSTATE_MAP_LOD_CONTROL
  225
- GFXRENDERSTATE_MAP_PALETTE_LOAD
  226
- GFXRENDERSTATE_MAP_COLOR_BLEND_STAGES
  227
- GFXRENDERSTATE_MAP_ALPHA_BLEND_STAGES
  230
- GFXRENDERSTATE_COLOR_FACTOR
  232
- GFXRENDERSTATE_COLOR_CHROMA_KEY
  233
- GFXRENDERSTATE_SRC_DST_BLEND_MONO
  235
- GFXRENDERSTATE_Z_BIAS_ALPHA_FUNC_REF
  238
- GFXRENDERSTATE_LINE_WIDTH_CULL_SHADE_ MODE
  239
- GFXRENDERSTATE_BOOLEAN_ENA_1
  241
- GFXRENDERSTATE_BOOLEAN_ENA_2
  242
- GFXRENDERSTATE_FOG_COLOR
  243
- GFXRENDERSTATE_DRAWING_RECTANGLE_INFO
  243
- GFXRENDERSTATE_SCISSOR_ENABLE
  245
- GFXRENDERSTATE_SCISSOR_RECTANGLE_INFO
  246
- Stipple Pattern
  247
- GFXRENDERSTATE_ANTI_ALIASING
  248
- GFXRENDERSTATE_PROVOKING_VTX_PIXELIZATION_RULE
  249
- GFXRENDERSTATE_DEST_BUFFER_VARIABLES
  251
- Programming Hints/Rules
  253
Clock Control Registers
257
- Programming Notes
  257
- DCLK_0D—Display Clock 0 Divisor Register
  258
- DCLK_1D—Display Clock 1 Divisor Register
  259
- DCLK_2D—Display Clock 2 Divisor Register
  260
- LCD_CLKD—LCD Clock Divisor Register
  261
- DCLK_0DS—Display & LCD Clock Divisor Select Register
  262
- PWR_CLKC—Power Management and Miscellaneous Clock Control
  264
Overlay Registers
265
- OV0ADD—Overlay 0 Register Update Address Register
  267
- DOV0STA—Display/Overlay 0 Status Register
  268
- Gamma Correction
  269
- Memory Offset Registers
  274
- Overlay Flip Instruction
  299
Instruction, Memory, and Interrupt Control Registers
301
- Instruction Control Registers
  301
- Interrupt Control Registers
  320
- Display Interface Control
  331
  - FW_BLC—FIFO Watermark and Burst Length Control
    331
LCD / TV-Out Register Description
333
- HTOTAL—Horizontal Total Register
  333
- HBLANK—Horizontal Blank Register
  334
- HSYNC—Horizontal Sync Register
  335
- VTOTAL—Vertical Total Register
  336
- VBLANK—Vertical Blank Register
  337
- VSYNC—Vertical Sync Register
  338
- LCDTV_C—LCD/TV-Out Control Register
  339
- OVRACT—Overlay Active Register
  342
- BCLRPAT— Border Color Pattern Register
  342
Local Memory Interface
343
- DRT—DRAM Row Type
  343
- DRAMCL—DRAM Control Low
  344
- DRAMCH—DRAM Control High
  345
I/O Control Registers
347
- HVSYNC—HSYNC/VSYNC Control Register
  347
- GPIO Registers
  348
  - GPIOA(General Purpose I/O Control Register A
    348
  - GPIOB(General Purpose I/O Control Register B
    350
Display And Cursor Registers
353
- DISP_SL—Display Scan Line Count
  353
- DISP_SLC—Display Scan Line Count Range Compare
  354
- Pixel Pipeline Control
  355
- Hardware Cursor
  361
Appendix A: Mode Parameters
363

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