Intel 253666-024US Benutzerhandbuch
3-162 Vol. 2A
CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-M
CPUID—CPU Identification
Description
The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruc-
tion. If a software procedure can set and clear this flag, the processor executing the
procedure supports the CPUID instruction. This instruction operates the same in non-
64-bit modes and 64-bit mode.
CPUID returns processor identification and feature information in the EAX, EBX, ECX,
and EDX registers.
tion. If a software procedure can set and clear this flag, the processor executing the
procedure supports the CPUID instruction. This instruction operates the same in non-
64-bit modes and 64-bit mode.
CPUID returns processor identification and feature information in the EAX, EBX, ECX,
and EDX registers.
1
The instruction’s output is dependent on the contents of the EAX
register upon execution (in some cases, ECX as well). For example, the following
pseudocode loads EAX with 00H and causes CPUID to return a Maximum Return
Value and the Vendor Identification String in the appropriate registers:
pseudocode loads EAX with 00H and causes CPUID to return a Maximum Return
Value and the Vendor Identification String in the appropriate registers:
MOV EAX, 00H
CPUID
CPUID
Table 3-12 shows information returned, depending on the initial value loaded into the
EAX register. Table 3-13 shows the maximum CPUID input value recognized for each
family of IA-32 processors on which CPUID is implemented.
Two types of information are returned: basic and extended function information. If a
value is entered for CPUID.EAX is invalid for a particular processor, the data for the
highest basic information leaf is returned. For example, using the Intel Core 2 Duo
processor, the following is true:
EAX register. Table 3-13 shows the maximum CPUID input value recognized for each
family of IA-32 processors on which CPUID is implemented.
Two types of information are returned: basic and extended function information. If a
value is entered for CPUID.EAX is invalid for a particular processor, the data for the
highest basic information leaf is returned. For example, using the Intel Core 2 Duo
processor, the following is true:
CPUID.EAX = 05H (* Returns MONITOR/MWAIT leaf. *)
CPUID.EAX = 0AH (* Returns Architectural Performance Monitoring leaf. *)
CPUID.EAX = 0BH (* INVALID: Returns the same information as CPUID.EAX = 0AH. *)
CPUID.EAX = 80000008H (* Returns virtual/physical address size data. *)
CPUID.EAX = 8000000AH (* INVALID: Returns same information as CPUID.EAX = 0AH. *)
CPUID.EAX = 0AH (* Returns Architectural Performance Monitoring leaf. *)
CPUID.EAX = 0BH (* INVALID: Returns the same information as CPUID.EAX = 0AH. *)
CPUID.EAX = 80000008H (* Returns virtual/physical address size data. *)
CPUID.EAX = 8000000AH (* INVALID: Returns same information as CPUID.EAX = 0AH. *)
CPUID can be executed at any privilege level to serialize instruction execution. Seri-
alizing instruction execution guarantees that any modifications to flags, registers,
and memory for previous instructions are completed before the next instruction is
fetched and executed.
alizing instruction execution guarantees that any modifications to flags, registers,
and memory for previous instructions are completed before the next instruction is
fetched and executed.
Opcode
Instruction
64-Bit Mode Compat/
Leg Mode
Description
0F A2
CPUID
Valid
Valid
Returns processor identification
and feature information to the
EAX, EBX, ECX, and EDX registers,
as determined by input entered in
EAX (in some cases, ECX as well).
1. On Intel 64 processors, CPUID clears the high 32 bits of the RAX/RBX/RCX/RDX registers in all
modes.