Intel 253666-024US Benutzerhandbuch

3-164 Vol. 2A

CPUID—CPU Identification

INSTRUCTION SET REFERENCE, A-M

CPUID leaves > 3 < 80000000 are visible only when 

IA32_MISC_ENABLES.BOOT_NT4[bit 22] = 0 (default).
Deterministic Cache Parameters Leaf 

04H

NOTES:

04H output depends on the initial value in ECX. 
See also: “INPUT EAX = 4: Returns Deterministic Cache Parameters 

for each level on page 3-180.

EAX

Bits 4-0: Cache Type Field

0 = Null - No more caches 3 = Unified Cache

1 = Data Cache 

4-31 = Reserved

2 = Instruction Cache

Bits 7-5: Cache Level (starts at 1) 

Bits 8: Self Initializing cache level (does not need SW initialization)

Bits 9: Fully Associative cache
Bit 10: Write-Back Invalidate/Invalidate

0 = WBINVD/INVD from threads sharing this cache acts upon lower 

level caches for threads sharing this cache

1 = WBINVD/INVD is not guaranteed to act upon lower level caches 

of non-originating threads sharing this cache.

Bit 11: Cache Inclusiveness

0 = Cache is not inclusive of lower cache levels.

1 = Cache is inclusive of lower cache levels.

Bits 13-12: Reserved

Bits 25-14: Maximum number of threads sharing this cache in a physi-

cal package* 

Bits 31-26: Maximum number of processor cores in the physical 

package* **

EBX

Bits 11-00: L = System Coherency Line Size*

Bits 21-12: P = Physical Line partitions*

Bits 31-22: W = Ways of associativity*

ECX

EDX

Bits 31-00: S = Number of Sets*

Reserved = 0

NOTES:

* Add one to the return value to get the result. 
** The returned value is constant for valid initial values in ECX. Valid 

ECX values start from 0. 

Table 3-12.  Information Returned by CPUID Instruction (Contd.)

Initial EAX 

Value

Information Provided about the Processor