Intel 253666-024US Benutzerhandbuch
3-392 Vol. 2A
FSTENV/FNSTENV—Store x87 FPU Environment
INSTRUCTION SET REFERENCE, A-M
FSTENV/FNSTENV—Store x87 FPU Environment
Description
Saves the current FPU operating environment at the memory location specified with
the destination operand, and then masks all floating-point exceptions. The FPU oper-
ating environment consists of the FPU control word, status word, tag word, instruc-
tion pointer, data pointer, and last opcode. Figures 8-9 through 8-12 in the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 1, show the layout in
memory of the stored environment, depending on the operating mode of the
processor (protected or real) and the current operand-size attribute (16-bit or
32-bit). In virtual-8086 mode, the real mode layouts are used.
The FSTENV instruction checks for and handles any pending unmasked floating-point
exceptions before storing the FPU environment; the FNSTENV instruction does
not. The saved image reflects the state of the FPU after all floating-point instructions
preceding the FSTENV/FNSTENV instruction in the instruction stream have been
executed.
These instructions are often used by exception handlers because they provide access
to the FPU instruction and data pointers. The environment is typically saved in the
stack. Masking all exceptions after saving the environment prevents floating-point
exceptions from interrupting the exception handler.
The assembler issues two instructions for the FSTENV instruction (an FWAIT instruc-
tion followed by an FNSTENV instruction), and the processor executes each of these
instructions separately. If an exception is generated for either of these instructions,
the save EIP points to the instruction that caused the exception.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
the destination operand, and then masks all floating-point exceptions. The FPU oper-
ating environment consists of the FPU control word, status word, tag word, instruc-
tion pointer, data pointer, and last opcode. Figures 8-9 through 8-12 in the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 1, show the layout in
memory of the stored environment, depending on the operating mode of the
processor (protected or real) and the current operand-size attribute (16-bit or
32-bit). In virtual-8086 mode, the real mode layouts are used.
The FSTENV instruction checks for and handles any pending unmasked floating-point
exceptions before storing the FPU environment; the FNSTENV instruction does
not. The saved image reflects the state of the FPU after all floating-point instructions
preceding the FSTENV/FNSTENV instruction in the instruction stream have been
executed.
These instructions are often used by exception handlers because they provide access
to the FPU instruction and data pointers. The environment is typically saved in the
stack. Masking all exceptions after saving the environment prevents floating-point
exceptions from interrupting the exception handler.
The assembler issues two instructions for the FSTENV instruction (an FWAIT instruc-
tion followed by an FNSTENV instruction), and the processor executes each of these
instructions separately. If an exception is generated for either of these instructions,
the save EIP points to the instruction that caused the exception.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
9B D9 /6
FSTENV m14/28byte Valid
Valid
Store FPU environment to m14byte
or m28byte after checking for
pending unmasked floating-point
exceptions. Then mask all floating-
point exceptions.
D9 /6
FNSTENV
*
m14/28byte
Valid
Valid
Store FPU environment to m14byte
or m28byte without checking for
pending unmasked floating-point
exceptions. Then mask all floating-
point exceptions.
NOTES:
* See IA-32 Architecture Compatibility section below.