Fujitsu FR81S Benutzerhandbuch
CHAPTER 19: BASE TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
56
3. When the down counter underflows, the UDIR bit of the base timer x timer control register
(BTxTMCR) of the even-number channels changes to "1". The channel configuration in 32-bit
timer mode is shown below.
Figure 5-11 Configuration in 32-bit Timer Mode
Notes:
⋅
The value of the down counter can be checked by reading the base timer x timer register (BTxTMR). In
the 32-bit timer mode, it must be read in the order of the lower 16-bit (even-numbered channel) → upper
16-bit (odd-number channel).
⋅
In 32-bit timer mode, the operation of the 32-bit reload timer conforms to the settings of the
even-number channels. Therefore, activation triggers and interrupt requests from even-number channels
are valid. The output signal (TOUT) from an odd-number channel pin is fixed to "L" level.
ch.1
ch.0
T32=1
T32=0
Underflow
Underflow
Upper 16-bit
Interrupt request
Lower 16-bit
Waveform output
Read/write signal
Lower 16-bit
Upper 16-bit
External activation trigger
reload value
reload value
down counter
down counter
MB91520 Series
MN705-00010-1v0-E
689