Freescale Semiconductor MPC8260 Benutzerhandbuch
Inverse Multiplexing for ATM (IMA)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
33-23
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The system is only capable of carrying services that either do not require CDV control (e.g. some
data services), or where the CDV is handled in some other way (e.g. absorbed in a play-out buffer
at the ATM layer connection termination).
data services), or where the CDV is handled in some other way (e.g. absorbed in a play-out buffer
at the ATM layer connection termination).
The PowerQUICC II may qualify as such a system, if the PowerQUICC II terminates all ATM connections
that it receives. The buffer-descriptors and external memory serve as a play-out buffer.
that it receives. The buffer-descriptors and external memory serve as a play-out buffer.
Furthermore, a system which does not terminate cells, but instead passes cells port-to-port, can also use
this mode of operation if either of the following conditions are met:
this mode of operation if either of the following conditions are met:
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All cell streams are switched at the VC level only, and the VC’s traffic type is one supported by the
PowerQUICC II’s APC. In this case, the APC of the PowerQUICC II can be programmed to
appropriately reshape the VC at the egress port, and therefore no cell delay variation (CDV) will
be introduced.
PowerQUICC II’s APC. In this case, the APC of the PowerQUICC II can be programmed to
appropriately reshape the VC at the egress port, and therefore no cell delay variation (CDV) will
be introduced.
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Some (or all) cell streams are switched at the VP level, but the switched VPs only carry traffic for
which cell delay variation (CDV) within the bounds of an IMA round-robin distribution is
tolerable. For example, if the IMA group consists of 8 DS1 links, then the maximum CDV
introduced by this method would be 8 cell times, or approximately 2.2ms
which cell delay variation (CDV) within the bounds of an IMA round-robin distribution is
tolerable. For example, if the IMA group consists of 8 DS1 links, then the maximum CDV
introduced by this method would be 8 cell times, or approximately 2.2ms
If the system meets the above qualifications, then this mode of operation is recommended, as it is the
simplest and will yield overall better system performance (i.e. this mode requires less CPM processing
power).
simplest and will yield overall better system performance (i.e. this mode requires less CPM processing
power).
33.3.3.2.2
IDCR-Regulated Cell Processing
In this mode, cell processing is triggered at the recovered IMA data cell rate (IDCR). During group startup,
the microcode recovers the PHY clock rate of the TRL from the average period between requests from the
TRL PHY. It does this by averaging the difference of timestamps taken from the IDCR master timer
whenever the TRL’s PHY is serviced. As part of the group activation process, software calculates the
required IDCR request rate (scaling this rate by the number of links in the IMA group and by the
2048/2049 scale factor introduced by stuffing on the TRL), programs it in the IMA group’s associated
entry in the IDCR timer table, and enables the group’s IDCR timer table entry. Whenever a link is added
or removed from the group, software must update the IDCR timer table entry.
the microcode recovers the PHY clock rate of the TRL from the average period between requests from the
TRL PHY. It does this by averaging the difference of timestamps taken from the IDCR master timer
whenever the TRL’s PHY is serviced. As part of the group activation process, software calculates the
required IDCR request rate (scaling this rate by the number of links in the IMA group and by the
2048/2049 scale factor introduced by stuffing on the TRL), programs it in the IMA group’s associated
entry in the IDCR timer table, and enables the group’s IDCR timer table entry. Whenever a link is added
or removed from the group, software must update the IDCR timer table entry.
The IDCR timer table entries are maintained by the CPM according to the IDCR master timer. For each
IDCR master timer tick, the IDCR timer table entries are updated. When an IDCR timer table entry times
out, it triggers cell processing for one cell from the delay compensation buffers of its associated IMA
group. The timer table entry is then reset according to its IDCR request rate.
IDCR master timer tick, the IDCR timer table entries are updated. When an IDCR timer table entry times
out, it triggers cell processing for one cell from the delay compensation buffers of its associated IMA
group. The timer table entry is then reset according to its IDCR request rate.
For this function to operate reliably and regularly, an adequate amount of CPM processing bandwidth must
be reserved for the microcode task that services the IDCR timers. If care is not taken with this aspect of
system design, then the IDCR task might miss the cell processing of incoming cells, resulting in the
eventual overflow of the delay compensation buffers. In order to ensure against this, it is recommended to
either (1) program the IDCR to run as a high-priority CPM task, or (2) leave an adequate margin of CPM
performance, on the order of 15%.
be reserved for the microcode task that services the IDCR timers. If care is not taken with this aspect of
system design, then the IDCR task might miss the cell processing of incoming cells, resulting in the
eventual overflow of the delay compensation buffers. In order to ensure against this, it is recommended to
either (1) program the IDCR to run as a high-priority CPM task, or (2) leave an adequate margin of CPM
performance, on the order of 15%.
One additional benefit from IDCR-regulated cell processing is the microcode support for IMA group
service timeouts. If an active IMA group experiences 3 IDCR tick timeouts without having a data cell
service timeouts. If an active IMA group experiences 3 IDCR tick timeouts without having a data cell