Benutzerhandbuch für Freescale Semiconductor MPC8260

Inhaltsverzeichnis

• MPC8260 PowerQUICC™ II Family Reference Manual

  1
• About This Book

  79
  • Reference Manual Revision History

    79
  • Before Using this Manual-Important Note

    81
  • Audience

    81
  • Organization

    81
  • Suggested Reading

    84
  • Conventions

    85
  • Acronyms and Abbreviations

    85
  • PowerPC Architecture Terminology Conventions

    89
• Part I Overview

  91
  • Intended Audience

    91
  • Contents

    91
  • Conventions

    91
  • Acronyms and Abbreviations

    92
• Chapter 1 Overview

  95
  • 1.1 Features

    95
  • 1.2 Architecture Overview

    100
    • Figure 1-1. PowerQUICC II Block Diagram

      101
    • 1.2.1 G2 Core

      101
    • 1.2.2 System Interface Unit (SIU)

      102
    • 1.2.3 Communications Processor Module (CPM)

      103
  • 1.3 Software Compatibility Issues

    103
    • 1.3.1 Signals

      104
      • Figure 1-2. PowerQUICC II External Signals

        105
  • 1.4 Differences between MPC860 and PowerQUICC II

    106
  • 1.5 Serial Protocol Table

    106
    • Table 1-1. PowerQUICC II Serial Protocols

      106
  • 1.6 PowerQUICC II Configurations

    107
    • 1.6.1 Pin Configurations

      107
    • 1.6.2 Serial Performance

      107
      • Table 1-2. Serial Performance

        107
      • Table 1-3. MPC8250 Serial Performance

        108
  • 1.7 Application Examples

    108
    • 1.7.1 Communication Systems

      108
      • 1.7.1.1 Remote Access Server

        108
        • Figure 1-3. Remote Access Server Configuration

          109
      • 1.7.1.2 Regional Office Router

        110
        • Figure 1-4. Regional Office Router Configuration

          110
      • 1.7.1.3 LAN-to-WAN Bridge Router

        110
        • Figure 1-5. LAN-to-WAN Bridge Router Configuration

          111
      • 1.7.1.4 Cellular Base Station

        111
        • Figure 1-6. Cellular Base Station Configuration

          111
      • 1.7.1.5 Telecommunications Switch Controller

        112
        • Figure 1-7. Telecommunications Switch Controller Configuration

          112
      • 1.7.1.6 SONET Transmission Controller

        112
        • Figure 1-8. SONET Transmission Controller Configuration

          113
    • 1.7.2 Bus Configurations

      113
      • 1.7.2.1 Basic System

        113
        • Figure 1-9. Basic System Configuration

          114
      • 1.7.2.2 High-Performance Communication

        114
        • Figure 1-10. High-Performance Communication

          114
      • 1.7.2.3 High-Performance System Microprocessor

        115
        • Figure 1-11. High-Performance System Microprocessor Configuration

          115
      • 1.7.2.4 PCI

        115
        • Figure 1-12. PCI Configuration

          116
      • 1.7.2.5 PCI with 155-Mbps ATM

        116
        • Figure 1-13. PCI with 155-Mbps ATM Configuration

          116
      • 1.7.2.6 PowerQUICC II as PCI Agent

        117
        • Figure 1-14. PowerQUICC II as PCI Agent

          117
• Chapter 2 G2 Core

  119
  • 2.1 Overview

    119
    • Figure 2-1. PowerQUICC II Integrated Processor Core Block Diagram

      120
  • 2.2 G2 Processor Core Features

    121
    • 2.2.1 Instruction Unit

      123
    • 2.2.2 Instruction Queue and Dispatch Unit

      123
    • 2.2.3 Branch Processing Unit (BPU)

      123
    • 2.2.4 Independent Execution Units

      124
      • 2.2.4.1 Integer Unit (IU)

        124
      • 2.2.4.2 Floating-Point Unit (FPU)

        124
      • 2.2.4.3 Load/Store Unit (LSU)

        124
      • 2.2.4.4 System Register Unit (SRU)

        125
    • 2.2.5 Completion Unit

      125
    • 2.2.6 Memory Subsystem Support

      125
      • 2.2.6.1 Memory Management Units (MMUs)

        125
      • 2.2.6.2 Cache Units

        126
  • 2.3 Programming Model

    126
    • 2.3.1 Register Set

      126
      • 2.3.1.1 PowerPC Register Set

        127
        • Figure 2-2. PowerQUICC II Programming Model-Registers

          128
      • 2.3.1.2 PowerQUICC II-Specific Registers

        129
        • 2.3.1.2.1 Hardware Implementation-Dependent Register 0 (HID0)

          129
          • Figure 2-3. Hardware Implementation Register 0 (HID0)

            129
          • Table 2-1. HID0 Field Descriptions (continued)

            129
        • 2.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1)

          132
          • Figure 2-4. Hardware Implementation-Dependent Register 1 (HID1)

            132
          • Table 2-2. HID1 Field Descriptions

            132
        • 2.3.1.2.3 Hardware Implementation-Dependent Register 2 (HID2)

          132
          • Figure 2-5. Hardware Implementation-Dependent Register 2 (HID2)

            132
          • Table 2-3. HID2 Field Descriptions (continued)

            132
        • 2.3.1.2.4 Processor Version Register (PVR)

          133
    • 2.3.2 PowerPC Instruction Set and Addressing Modes

      133
      • 2.3.2.1 Calculating Effective Addresses

        133
      • 2.3.2.2 PowerPC Instruction Set

        134
      • 2.3.2.3 PowerQUICC II Implementation-Specific Instruction Set

        135
  • 2.4 Cache Implementation

    135
    • 2.4.1 PowerPC Cache Model

      136
    • 2.4.2 PowerQUICC II Implementation-Specific Cache Implementation

      136
      • 2.4.2.1 Data Cache

        136
        • Figure 2-6. Data Cache Organization

          137
      • 2.4.2.2 Instruction Cache

        138
      • 2.4.2.3 Cache Locking

        138
        • 2.4.2.3.1 Entire Cache Locking

          138
        • 2.4.2.3.2 Way Locking

          138
  • 2.5 Exception Model

    139
    • 2.5.1 PowerPC Exception Model

      139
    • 2.5.2 PowerQUICC II Implementation-Specific Exception Model

      140
      • Table 2-4. Exception Classifications for the Processor Core

        140
      • Table 2-5. Exceptions and Conditions (continued)

        140
    • 2.5.3 Exception Priorities

      143
  • 2.6 Memory Management

    143
    • 2.6.1 PowerPC MMU Model

      143
    • 2.6.2 PowerQUICC II Implementation-Specific MMU Features

      144
  • 2.7 Instruction Timing

    145
    • Table 2-6. Integer Divide Latency

      145
  • 2.8 Differences between the PowerQUICC II’s G2 Core and the MPC603e Microprocessor

    146
    • Table 2-7. Major Differences between PowerQUICC II’s G2 Core and the MPC603e User’s Manual

      146
• Chapter 3 Memory Map

  147
  • Table 3-1. Internal Memory Map

    147
• Part II Configuration and Reset

  171
  • Intended Audience

    171
  • Contents

    171
  • Suggested Reading

    171
  • Conventions

    171
  • Acronyms and Abbreviations

    172
• Chapter 4 System Interface Unit (SIU)

  173
  • Figure 4-1. SIU Block Diagram

    173
  • 4.1 System Configuration and Protection

    174
    • Table 4-1. System Configuration and Protection Functions

      174
    • Figure 4-2. System Configuration and Protection Logic

      175
    • 4.1.1 Bus Monitor

      175
    • 4.1.2 Timers Clock

      175
      • Figure 4-3. Timers Clock Generation

        176
    • 4.1.3 Time Counter (TMCNT)

      176
      • Figure 4-4. TMCNT Block Diagram

        177
    • 4.1.4 Periodic Interrupt Timer (PIT)

      177
      • Figure 4-5. PIT Block Diagram

        177
    • 4.1.5 Software Watchdog Timer

      178
      • Figure 4-6. Software Watchdog Timer Service State Diagram

        178
      • Figure 4-7. Software Watchdog Timer Block Diagram

        179
  • 4.2 Interrupt Controller

    179
    • 4.2.1 Interrupt Configuration

      180
      • Figure 4-8. PowerQUICC II Interrupt Structure

        180
      • 4.2.1.1 Machine Check Interrupt

        181
      • 4.2.1.2 INT Interrupt

        181
    • 4.2.2 Interrupt Source Priorities

      181
      • Table 4-2. Interrupt Source Priority Levels (continued)

        182
      • 4.2.2.1 SCC, FCC, and MCC Relative Priority

        184
      • 4.2.2.2 PIT, TMCNT, PCI, and IRQ Relative Priority

        185
      • 4.2.2.3 Highest Priority Interrupt

        185
    • 4.2.3 Masking Interrupt Sources

      185
      • Figure 4-9. Interrupt Request Masking

        186
    • 4.2.4 Interrupt Vector Generation and Calculation

      186
      • Table 4-3. Encoding the Interrupt Vector (continued)

        186
      • 4.2.4.1 Port C External Interrupts

        188
  • 4.3 Programming Model

    189
    • 4.3.1 Interrupt Controller Registers

      189
      • 4.3.1.1 SIU Interrupt Configuration Register (SICR)

        189
        • Figure 4-10. SIU Interrupt Configuration Register (SICR)

          189
        • Table 4-4. SICR Field Descriptions

          190
      • 4.3.1.2 SIU Interrupt Priority Register (SIPRR)

        190
        • Figure 4-11. SIU Interrupt Priority Register (SIPRR)

          190
        • Table 4-5. SIPRR Field Descriptions

          191
      • 4.3.1.3 CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L)

        191
        • Figure 4-12. CPM High Interrupt Priority Register (SCPRR_H)

          191
        • Table 4-6. SCPRR_H Field Descriptions

          192
        • Figure 4-13. CPM Low Interrupt Priority Register (SCPRR_L)

          192
        • Table 4-7. SCPRR_L Field Descriptions

          193
      • 4.3.1.4 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L)

        193
        • Figure 4-14. SIPNR_H

          193
        • Figure 4-15. SIPNR_L

          194
      • 4.3.1.5 SIU Interrupt Mask Registers (SIMR_H and SIMR_L)

        194
        • Figure 4-16. SIMR_H

          195
        • Figure 4-17. SIMR_L

          195
      • 4.3.1.6 SIU Interrupt Vector Register (SIVEC)

        196
        • Figure 4-18. SIU Interrupt Vector Register (SIVEC)

          196
        • Figure 4-19. Interrupt Table Handling Example

          197
      • 4.3.1.7 SIU External Interrupt Control Register (SIEXR)

        197
        • Figure 4-20. SIU External Interrupt Control Register (SIEXR)

          198
        • Table 4-8. SIEXR Field Descriptions

          198
    • 4.3.2 System Configuration and Protection Registers

      198
      • 4.3.2.1 Bus Configuration Register (BCR)

        198
        • Figure 4-21. Bus Configuration Register (BCR)

          199
        • Table 4-9. BCR Field Descriptions (continued)

          199
      • 4.3.2.2 60x Bus Arbiter Configuration Register (PPC_ACR)

        201
        • Figure 4-22. PPC_ACR

          201
        • Table 4-10. PPC_ACR Field Descriptions

          202
      • 4.3.2.3 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL)

        202
        • Figure 4-23. PPC_ALRH

          202
        • Figure 4-24. PPC_ALRL

          203
      • 4.3.2.4 Local Bus Arbiter Configuration Register (LCL_ACR)

        203
        • Figure 4-25. LCL_ACR

          203
        • Table 4-11. LCL_ACR Field Descriptions (continued)

          203
      • 4.3.2.5 Local Bus Arbitration Level Registers (LCL_ALRH and LCL_ACRL)

        204
        • Figure 4-26. LCL_ALRH

          204
        • Figure 4-27. LCL_ALRL

          205
      • 4.3.2.6 SIU Module Configuration Register (SIUMCR)

        205
        • Figure 4-28. SIU Model Configuration Register (SIUMCR)

          205
        • Table 4-12. SIUMCR Register Field Descriptions (continued)

          205
      • 4.3.2.7 Internal Memory Map Register (IMMR)

        208
        • Figure 4-29. Internal Memory Map Register (IMMR)

          208
        • Table 4-13. IMMR Field Descriptions

          209
      • 4.3.2.8 System Protection Control Register (SYPCR)

        209
        • Figure 4-30. System Protection Control Register (SYPCCR)

          209
        • Table 4-14. SYPCR Field Descriptions

          210
      • 4.3.2.9 Software Service Register (SWSR)

        210
      • 4.3.2.10 60x Bus Transfer Error Status and Control Register 1 (TESCR1)

        210
        • Figure 4-31. 60x Bus Transfer Error Status and Control Register 1 (TESCR1)

          211
        • Table 4-15. TESCR1 Field Descriptions (continued)

          211
      • 4.3.2.11 60x Bus Transfer Error Status and Control Register 2 (TESCR2)

        212
        • Figure 4-32. 60x Bus Transfer Error Status and Control Register 2 (TESCR2)

          213
        • Table 4-16. TESCR2 Field Descriptions

          213
      • 4.3.2.12 Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)

        214
        • Figure 4-33. Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)

          214
        • Table 4-17. L_TESCR1 Field Descriptions (continued)

          214
      • 4.3.2.13 Local Bus Transfer Error Status and Control Register 2 (L_TESCR2)

        215
        • Figure 4-34. Local Bus Transfer Error Status and Control Register 2 (L_TESCR2)

          215
        • Table 4-18. L_TESCR2 Field Descriptions

          215
      • 4.3.2.14 Time Counter Status and Control Register (TMCNTSC)

        216
        • Figure 4-35. Time Counter Status and Control Register (TMCNTSC)

          216
        • Table 4-19. TMCNTSC Field Descriptions

          216
      • 4.3.2.15 Time Counter Register (TMCNT)

        216
        • Figure 4-36. Time Counter Register (TCMCNT)

          217
      • 4.3.2.16 Time Counter Alarm Register (TMCNTAL)

        217
        • Figure 4-37. Time Counter Alarm Register (TMCNTAL)

          217
        • Table 4-20. TMCNTAL Field Descriptions

          217
    • 4.3.3 Periodic Interrupt Registers

      218
      • 4.3.3.1 Periodic Interrupt Status and Control Register (PISCR)

        218
        • Figure 4-38. Periodic Interrupt Status and Control Register (PISCR)

          218
        • Table 4-21. PISCR Field Descriptions

          218
      • 4.3.3.2 Periodic Interrupt Timer Count Register (PITC)

        218
        • Figure 4-39. Periodic interrupt Timer Count Register (PITC)

          219
        • Table 4-22. PITC Field Descriptions

          219
      • 4.3.3.3 Periodic Interrupt Timer Register (PITR)

        219
        • Figure 4-40. Periodic Interrupt Timer Register (PITR)

          219
        • Table 4-23. PITR Field Descriptions

          220
    • 4.3.4 PCI Control Registers

      220
      • 4.3.4.1 PCI Base Register (PCIBRx)

        220
        • Figure 4-41. PCI Base Registers (PCIBRx)

          220
        • Table 4-24. PCIBRx Field Descriptions

          221
      • 4.3.4.2 PCI Mask Register (PCIMSKx)

        221
        • Figure 4-42. PCI Mask Register (PCIMSKx)

          221
        • Table 4-25. PCIMSKx Field Descriptions

          221
  • 4.4 SIU Pin Multiplexing

    221
    • Table 4-26. SIU Pins Multiplexing Control

      222
• Chapter 5 Reset

  223
  • 5.1 Reset Causes

    223
    • Table 5-1. Reset Causes

      223
    • 5.1.1 Reset Actions

      224
      • Table 5-2. Reset Actions for Each Reset Source

        224
    • 5.1.2 Power-On Reset Flow

      224
      • Figure 5-1. Power-on Reset Flow

        225
    • 5.1.3 HRESET Flow

      225
    • 5.1.4 SRESET Flow

      225
  • 5.2 Reset Status Register (RSR)

    226
    • Figure 5-2. Reset Status Register (RSR)

      226
    • Table 5-3. RSR Field Descriptions (continued)

      226
  • 5.3 Reset Mode Register (RMR)

    227
    • Figure 5-3. Reset Mode Register (RMR)

      227
    • Table 5-4. RMR Field Descriptions

      228
  • 5.4 Reset Configuration

    228
    • Table 5-5. RSTCONF Connections in Multiple-PowerQUICC II Systems (continued)

      228
    • Table 5-6. Configuration EPROM Addresses

      229
    • 5.4.1 Hard Reset Configuration Word

      230
      • Figure 5-4. Hard Reset Configuration Word

        230
      • Table 5-7. Hard Reset Configuration Word Field Descriptions (continued)

        230
    • 5.4.2 Hard Reset Configuration Examples

      232
      • 5.4.2.1 Single PowerQUICC II with Default Configuration

        232
        • Figure 5-5. Single Chip with Default Configuration

          232
      • 5.4.2.2 Single PowerQUICC II Configured from Boot EPROM

        232
        • Figure 5-6. Configuring a Single Chip from EPROM

          233
      • 5.4.2.3 Multiple PowerQUICC IIs Configured from Boot EPROM

        233
        • Figure 5-7. Configuring Multiple Chips

          234
      • 5.4.2.4 Multiple PowerQUICC IIs in a System with No EPROM

        235
• Part III The Hardware Interface

  237
  • Intended Audience

    237
  • Contents

    237
  • Suggested Reading

    237
  • Conventions

    238
  • Acronyms and Abbreviations

    238
• Chapter 6 External Signals

  241
  • 6.1 Functional Pinout

    241
    • Figure 6-1. PowerQUICC II External Signals

      242
  • 6.2 Signal Descriptions

    242
    • Table 6-1. External Signals (continued)

      243
• Chapter 7 60x Signals

  257
  • 7.1 Signal Configuration

    258
    • Figure 7-1. Signal Groupings

      258
  • 7.2 Signal Descriptions

    258
    • 7.2.1 Address Bus Arbitration Signals

      259
      • 7.2.1.1 Bus Request (BR)-Output

        259
        • 7.2.1.1.1 Address Bus Request (BR)-Output

          259
        • 7.2.1.1.2 Address Bus Request (BR)-Input

          259
      • 7.2.1.2 Bus Grant (BG)

        260
        • 7.2.1.2.1 Bus Grant (BG)-Input

          260
        • 7.2.1.2.2 Bus Grant (BG)-Output

          260
      • 7.2.1.3 Address Bus Busy (ABB)

        261
        • 7.2.1.3.1 Address Bus Busy (ABB)-Output

          261
        • 7.2.1.3.2 Address Bus Busy (ABB)-Input

          261
    • 7.2.2 Address Transfer Start Signal

      261
      • 7.2.2.1 Transfer Start (TS)

        261
        • 7.2.2.1.1 Transfer Start (TS)-Output

          261
      • 7.2.2.2 Transfer Start (TS)-Input

        262
    • 7.2.3 Address Transfer Signals

      262
      • 7.2.3.1 Address Bus (A[0-31])

        262
        • 7.2.3.1.1 Address Bus (A[0-31])-Output

          262
        • 7.2.3.1.2 Address Bus (A[0-31])-Input

          262
    • 7.2.4 Address Transfer Attribute Signals

      263
      • 7.2.4.1 Transfer Type (TT[0-4])

        263
        • 7.2.4.1.1 Transfer Type (TT[0-4])-Output

          263
        • 7.2.4.1.2 Transfer Type (TT[0-4])-Input

          263
      • 7.2.4.2 Transfer Size (TSIZ[0-3])

        263
      • 7.2.4.3 Transfer Burst (TBST)

        264
      • 7.2.4.4 Global (GBL)

        264
        • 7.2.4.4.1 Global (GBL)-Output

          264
        • 7.2.4.4.2 Global (GBL)-Input

          264
      • 7.2.4.5 Caching-Inhibited (CI)-Output

        264
      • 7.2.4.6 Write-Through (WT)-Output

        265
    • 7.2.5 Address Transfer Termination Signals

      265
      • 7.2.5.1 Address Acknowledge (AACK)

        265
        • 7.2.5.1.1 Address Acknowledge (AACK)-Output

          265
        • 7.2.5.1.2 Address Acknowledge (AACK)-Input

          265
      • 7.2.5.2 Address Retry (ARTRY)

        266
        • 7.2.5.2.1 Address Retry (ARTRY)-Output

          266
        • 7.2.5.2.2 Address Retry (ARTRY)-Input

          266
    • 7.2.6 Data Bus Arbitration Signals

      267
      • 7.2.6.1 Data Bus Grant (DBG)

        267
        • 7.2.6.1.1 Data Bus Grant (DBG)-Input

          267
        • 7.2.6.1.2 Data Bus Grant (DBG)-Output

          267
      • 7.2.6.2 Data Bus Busy (DBB)

        268
        • 7.2.6.2.1 Data Bus Busy (DBB)-Output

          268
        • 7.2.6.2.2 Data Bus Busy (DBB)-Input

          268
    • 7.2.7 Data Transfer Signals

      268
      • 7.2.7.1 Data Bus (D[0-63])

        268
        • 7.2.7.1.1 Data Bus (D[0-63])-Output

          269
          • Table 7-1. Data Bus Lane Assignments

            269
        • 7.2.7.1.2 Data Bus (D[0-63])-Input

          269
      • 7.2.7.2 Data Bus Parity (DP[0-7])

        269
        • 7.2.7.2.1 Data Bus Parity (DP[0-7])-Output

          269
          • Table 7-2. DP[0-7] Signal Assignments

            270
        • 7.2.7.2.2 Data Bus Parity (DP[0-7])-Input

          270
    • 7.2.8 Data Transfer Termination Signals

      270
      • 7.2.8.1 Transfer Acknowledge (TA)

        270
        • 7.2.8.1.1 Transfer Acknowledge (TA)-Input

          270
        • 7.2.8.1.2 Transfer Acknowledge (TA)-Output

          271
      • 7.2.8.2 Transfer Error Acknowledge (TEA)

        272
        • 7.2.8.2.1 Transfer Error Acknowledge (TEA)-Input

          272
        • 7.2.8.2.2 Transfer Error Acknowledge (TEA)-Output

          272
      • 7.2.8.3 Partial Data Valid Indication (PSDVAL)

        272
        • 7.2.8.3.1 Partial Data Valid (PSDVAL)-Input

          272
        • 7.2.8.3.2 Partial Data Valid (PSDVAL)-Output

          273
• Chapter 8 The 60x Bus

  275
  • 8.1 Terminology

    275
    • Table 8-1. Terminology (continued)

      275
  • 8.2 Bus Configuration

    276
    • 8.2.1 Single-PowerQUICC II Bus Mode

      276
      • Figure 8-1. Single-PowerQUICC II Bus Mode

        277
    • 8.2.2 60x-Compatible Bus Mode

      277
      • Figure 8-2. 60x-Compatible Bus Mode

        278
  • 8.3 60x Bus Protocol Overview

    278
    • Figure 8-3. Basic Transfer Protocol

      279
    • 8.3.1 Arbitration Phase

      279
    • 8.3.2 Address Pipelining and Split-Bus Transactions

      280
  • 8.4 Address Tenure Operations

    281
    • 8.4.1 Address Arbitration

      281
      • Figure 8-4. Address Bus Arbitration with External Bus Master

        282
    • 8.4.2 Address Pipelining

      282
      • Figure 8-5. Address Pipelining

        283
    • 8.4.3 Address Transfer Attribute Signals

      283
      • 8.4.3.1 Transfer Type Signal (TT[0-4]) Encoding

        283
        • Table 8-2. Transfer Type Encoding (continued)

          284
      • 8.4.3.2 Transfer Code Signals TC[0-2]

        286
        • Table 8-3. Transfer Code Encoding for 60x Bus

          286
      • 8.4.3.3 TBST and TSIZ[0-3] Signals and Size of Transfer

        286
        • Table 8-4. Transfer Size Signal Encoding

          287
      • 8.4.3.4 Burst Ordering During Data Transfers

        287
        • Table 8-5. Burst Ordering

          288
      • 8.4.3.5 Effect of Alignment on Data Transfers

        288
        • Table 8-6. Aligned Data Transfers (continued)

          288
        • Table 8-7. Unaligned Data Transfer Example (4-Byte Example) (continued)

          289
      • 8.4.3.6 Effect of Port Size on Data Transfers

        290
        • Figure 8-6. Interface to Different Port Size Devices

          291
        • Table 8-8. Data Bus: Read Cycle Requirements and Write Cycle Content

          292
      • 8.4.3.7 60x-Compatible Bus Mode-Size Calculation

        292
        • Table 8-9. Address and Size State Calculations

          293
      • 8.4.3.8 Extended Transfer Mode

        293
        • Table 8-10. Data Bus Contents for Extended Write Cycles

          294
        • Table 8-11. Data Bus Requirements for Extended Read Cycles

          294
        • Table 8-12. Address and Size State for Extended Transfers (continued)

          295
    • 8.4.4 Address Transfer Termination

      296
      • 8.4.4.1 Address Retried with ARTRY

        296
        • Figure 8-7. Retry Cycle

          297
      • 8.4.4.2 Address Tenure Timing Configuration

        298
    • 8.4.5 Pipeline Control

      298
  • 8.5 Data Tenure Operations

    299
    • 8.5.1 Data Bus Arbitration

      299
    • 8.5.2 Data Streaming Mode

      300
    • 8.5.3 Data Bus Transfers and Normal Termination

      300
      • Figure 8-8. Single-Beat and Burst Data Transfers

        301
    • 8.5.4 Effect of ARTRY Assertion on Data Transfer and Arbitration

      301
    • 8.5.5 Port Size Data Bus Transfers and PSDVAL Termination

      301
      • Figure 8-9. 28-Bit Extended Transfer to 32-Bit Port Size

        302
      • Figure 8-10. Burst Transfer to 32-Bit Port Size

        303
    • 8.5.6 Data Bus Termination by Assertion of TEA

      303
      • Figure 8-11. Data Tenure Terminated by Assertion of TEA

        304
  • 8.6 Memory Coherency-MEI Protocol

    304
    • Figure 8-12. MEI Cache Coherency Protocol-State Diagram (WIM = 001)

      305
  • 8.7 Processor State Signals

    305
    • 8.7.1 Support for the lwarx/stwcx. Instruction Pair

      306
    • 8.7.2 TLBISYNC Input

      306
  • 8.8 Little-Endian Mode

    306
• Chapter 9 PCI Bridge

  307
  • Figure 9-1. PCI Bridge in the PowerQUICC II

    308
  • Figure 9-2. PCI Bridge Structure

    308
  • 9.1 Signals

    309
  • 9.2 Clocking

    309
  • 9.3 PCI Bridge Initialization

    309
  • 9.4 SDMA Interface

    309
  • 9.5 Interrupts from PCI Bridge

    310
  • 9.6 60x Bus Arbitration Priority

    310
  • 9.7 60x Bus Masters

    310
  • 9.8 CompactPCI Hot Swap Specification Support

    311
  • 9.9 PCI Interface

    311
    • Table 9-1. PCI Terminology

      312
    • 9.9.1 PCI Interface Operation

      312
      • 9.9.1.1 Bus Commands

        312
        • Table 9-2. PCI Command Definitions

          313
      • 9.9.1.2 PCI Protocol Fundamentals

        313
        • 9.9.1.2.1 Basic Transfer Control

          314
        • 9.9.1.2.2 Addressing

          314
        • 9.9.1.2.3 Byte Enable Signals

          315
        • 9.9.1.2.4 Bus Driving and Turnaround

          315
      • 9.9.1.3 Bus Transactions

        315
        • 9.9.1.3.1 Read and Write Transactions

          315
          • Figure 9-3. Single Beat Read Example

            316
          • Figure 9-4. Burst Read Example

            316
          • Figure 9-5. Single Beat Write Example

            317
          • Figure 9-6. Burst Write Example

            317
        • 9.9.1.3.2 Transaction Termination

          317
          • Figure 9-7. Target-Initiated Terminations

            318
      • 9.9.1.4 Other Bus Operations

        319
        • 9.9.1.4.1 Device Selection

          319
        • 9.9.1.4.2 Fast Back-to-Back Transactions

          320
        • 9.9.1.4.3 Data Streaming

          320
        • 9.9.1.4.4 Host Mode Configuration Access

          321
          • Figure 9-8. PCI Configuration Type 0 Translation (Top = CONFIG_ADDR) (Bottom = PCI Address Lines)

            321
        • 9.9.1.4.5 Agent Mode Configuration Access

          322
        • 9.9.1.4.6 Special Cycle Command

          322
        • 9.9.1.4.7 Interrupt Acknowledge

          323
      • 9.9.1.5 Error Functions

        323
        • 9.9.1.5.1 Parity

          323
        • 9.9.1.5.2 Error Reporting

          324
          • Figure 9-9. PCI Parity Operation

            324
    • 9.9.2 PCI Bus Arbitration

      325
      • 9.9.2.1 Bus Parking

        325
      • 9.9.2.2 Arbitration Algorithm

        325
        • Figure 9-10. PCI Arbitration Example

          326
      • 9.9.2.3 Master Latency Timer

        326
  • 9.10 Address Map

    327
    • Figure 9-11. Address Decode Flow Chart for 60x Bus Mastered Transactions

      327
    • Figure 9-12. Address Decode Flow Chart for PCI Mastered Transactions

      328
    • Figure 9-13. Address Decode Flow Chart for Embedded Utilities (DMA, Message Unit) Mastered Transactions

      329
    • Figure 9-14. Address Map Example

      330
    • 9.10.1 Address Map Programming

      330
    • 9.10.2 Address Translation

      330
      • 9.10.2.1 PCI Inbound Translation

        331
        • Figure 9-15. Inbound PCI Memory Address Translation

          331
      • 9.10.2.2 PCI Outbound Translation

        332
        • Figure 9-16. Outbound PCI Memory Address Translation

          332
    • 9.10.3 SIU Registers

      332
  • 9.11 Configuration Registers

    333
    • 9.11.1 Memory-Mapped Configuration Registers

      333
      • Table 9-3. Internal Memory Map (continued)

        333
      • 9.11.1.1 Message Unit (I2O) Registers

        336
      • 9.11.1.2 DMA Controller Registers

        336
      • 9.11.1.3 PCI Outbound Translation Address Registers (POTARx)

        336
        • Figure 9-17. PCI Outbound Translation Address Registers (POTARx)

          336
        • Table 9-4. POTARx Field Descriptions

          337
      • 9.11.1.4 PCI Outbound Base Address Registers (POBARx)

        337
        • Figure 9-18. PCI Outbound Base Address Registers (POBARx)

          337
        • Table 9-5. POBARx Field Descriptions

          337
      • 9.11.1.5 PCI Outbound Comparison Mask Registers (POCMRx)

        337
        • Figure 9-19. PCI Outbound Comparison Mask Registers (POCMRx)

          338
        • Table 9-6. POCMRx Field Descriptions

          338
      • 9.11.1.6 Discard Timer Control Register (PTCR)

        338
        • Figure 9-20. Discard Timer Control register (PTCR)

          339
        • Table 9-7. PTCR Field Descriptions

          339
      • 9.11.1.7 General Purpose Control Register (GPCR)

        339
        • Figure 9-21. General Purpose Control Register (GPCR)

          340
        • Table 9-8. GPCR Field Descriptions (continued)

          340
      • 9.11.1.8 PCI General Control Register (PCI_GCR)

        341
        • Figure 9-22. PCI General Control Register (PCI_GCR)

          341
        • Table 9-9. PCI_GCR Field Descriptions

          341
      • 9.11.1.9 Error Status Register (ESR)

        341
        • Figure 9-23. Error Status Register (ESR)

          342
        • Table 9-10. ESR Field Descriptions (continued)

          342
      • 9.11.1.10 Error Mask Register (EMR)

        343
        • Figure 9-24. Error Mask Register (EMR)

          343
        • Table 9-11. EMR Field Descriptions (continued)

          343
      • 9.11.1.11 Error Control Register (ECR)

        344
        • Figure 9-25. Error Control Register (ECR)

          344
        • Table 9-12. ECR Field Descriptions

          345
      • 9.11.1.12 PCI Error Address Capture Register (PCI_EACR)

        345
        • Figure 9-26. PCI Error Address Capture Register (PCI_EACR)

          345
        • Table 9-13. PCI_EACR Field Descriptions

          346
      • 9.11.1.13 PCI Error Data Capture Register (PCI_EDCR)

        346
        • Figure 9-27. PCI Error Data Capture Register (PCI_EDCR)

          346
        • Table 9-14. PCI_EDCR Field Description

          346
      • 9.11.1.14 PCI Error Control Capture Register (PCI_ECCR)

        346
        • Figure 9-28. PCI Error Control Capture Register (PCI_ECCR)

          347
        • Table 9-15. PCI_ECCR Field Descriptions (continued)

          347
      • 9.11.1.15 PCI Inbound Translation Address Registers (PITARx)

        348
        • Figure 9-29. PCI Inbound Translation Address Registers (PITARx)

          348
        • Table 9-16. PITARx Field Descriptions

          348
      • 9.11.1.16 PCI Inbound Base Address Registers (PIBARx)

        348
        • Figure 9-30. PCI Inbound Base Address Registers (PIBARx)

          349
      • 9.11.1.17 PCI Inbound Comparison Mask Registers (PICMRx)

        349
        • Table 9-17. PIBARx Field Descriptions

          349
        • Figure 9-31. PCI Inbound Comparison Mask Registers (PICMRx)

          350
        • Table 9-18. PICMRx Field Descriptions

          350
    • 9.11.2 PCI Bridge Configuration Registers

      351
      • Table 9-19. PCI Bridge PCI Configuration Registers (continued)

        351
      • Figure 9-32. PCI Bridge PCI Configuration Registers

        352
      • 9.11.2.1 Vendor ID Register

        352
        • Figure 9-33. Vendor ID Register

          353
        • Table 9-20. Vendor ID Register Description

          353
      • 9.11.2.2 Device ID Register

        353
        • Figure 9-34. Device ID Register

          353
        • Table 9-21. Device ID Register Description

          353
      • 9.11.2.3 PCI Bus Command Register

        353
        • Figure 9-35. PCI Bus Command Register

          353
        • Table 9-22. PCI Bus Command Register Description

          354
      • 9.11.2.4 PCI Bus Status Register

        354
        • Figure 9-36. PCI Bus Status Register

          355
        • Table 9-23. PCI Bus Status Register Description

          355
      • 9.11.2.5 Revision ID Register

        355
        • Figure 9-37. Revision ID Register

          356
        • Table 9-24. Revision ID Register Description

          356
      • 9.11.2.6 PCI Bus Programming Interface Register

        356
        • Figure 9-38. PCI Bus Programming Interface Register

          356
        • Table 9-25. PCI Bus Programming Interface Register Description

          356
      • 9.11.2.7 Subclass Code Register

        356
        • Figure 9-39. Subclass Code Register

          357
        • Table 9-26. Subclass Code Register Description

          357
      • 9.11.2.8 PCI Bus Base Class Code Register

        357
        • Figure 9-40. PCI Bus Base Class Code Register

          357
        • Table 9-27. PCI Bus Base Class Code Register Description

          357
      • 9.11.2.9 PCI Bus Cache Line Size Register

        357
        • Figure 9-41. PCI Bus Cache Line Size Register

          358
        • Table 9-28. PCI Bus Cache Line Size Register Description

          358
      • 9.11.2.10 PCI Bus Latency Timer Register

        358
        • Figure 9-42. PCI Bus Latency Timer Register

          358
        • Table 9-29. PCI Bus Latency Timer Register Description

          358
      • 9.11.2.11 Header Type Register

        358
        • Figure 9-43. Header Type Register

          359
        • Table 9-30. Header Type Register Description

          359
      • 9.11.2.12 BIST Control Register

        359
        • Figure 9-44. BIST Control Register

          359
        • Table 9-31. BIST Control Register Description

          359
      • 9.11.2.13 PCI Bus Internal Memory-Mapped Registers Base Address Register (PIMMRBAR)

        359
        • Figure 9-45. PCI Bus Internal Memory-Mapped Registers Base Address Register (PIMMRBAR)

          360
        • Table 9-32. PIMMRBAR Field Descriptions

          360
      • 9.11.2.14 General Purpose Local Access Base Address Registers (GPLABARx)

        360
        • Figure 9-46. General Purpose Local Access Base Address Registers (GPLABARx)

          361
        • Table 9-33. GPLABARx Field Descriptions

          361
      • 9.11.2.15 Subsystem Vendor ID Register

        361
        • Figure 9-47. Subsystem Vendor ID Register

          361
        • Table 9-34. Subsystem Vendor ID Register Description

          362
      • 9.11.2.16 Subsystem Device ID Register

        362
        • Figure 9-48. Subsystem Device ID Register

          362
        • Table 9-35. Subsystem Device ID Description Register

          362
      • 9.11.2.17 PCI Bus Capabilities Pointer Register

        362
        • Figure 9-49. PCI Bus Capabilities Pointer Register

          362
        • Table 9-36. PCI Bus Capabilities Pointer Register Description

          362
      • 9.11.2.18 PCI Bus Interrupt Line Register

        362
        • Figure 9-50. PCI Bus Interrupt Line Register

          363
        • Table 9-37. PCI Bus Interrupt Line Register Description

          363
      • 9.11.2.19 PCI Bus Interrupt Pin Register

        363
        • Figure 9-51. PCI Bus Interrupt Pin Register

          363
        • Table 9-38. PCI Bus Interrupt Pin Register Description

          363
      • 9.11.2.20 PCI Bus MIN GNT

        363
        • Figure 9-52. PCI Bus MIN GNT

          363
        • Table 9-39. PCI Bus MIN GNT Description

          364
      • 9.11.2.21 PCI Bus MAX LAT

        364
        • Figure 9-53. PCI Bus MAX LAT

          364
        • Table 9-40. PCI Bus MAX LAT Description

          364
      • 9.11.2.22 PCI Bus Function Register

        364
        • Figure 9-54. PCI Bus Function Register

          364
        • Table 9-41. PCI Bus Function Register Field Descriptions

          365
      • 9.11.2.23 PCI Bus Arbiter Configuration Register

        365
        • Figure 9-55. PCI Bus Arbiter Configuration Register

          365
        • Table 9-42. PCI Bus Arbiter Configuration Register Field Description

          366
      • 9.11.2.24 PCI Hot Swap Register Block

        366
        • Figure 9-56. Hot Swap Register Block

          366
        • Table 9-43. Hot Swap Register Block Field Descriptions

          367
      • 9.11.2.25 PCI Hot Swap Control Status Register

        367
        • Figure 9-57. Hot Swap Control Status Register

          367
        • Table 9-44. Hot Swap Control Status Register Field Descriptions

          367
      • 9.11.2.26 PCI Configuration Register Access from the Core

        368
      • 9.11.2.27 PCI Configuration Register Access in Big-Endian Mode

        368
        • 9.11.2.27.1 Additional Information on Endianess

          369
        • 9.11.2.27.2 Notes on GPCR[LE_MODE]

          369
      • 9.11.2.28 Initializing the PCI Configuration Registers

        370
        • Figure 9-58. Data Structure for Register Initialization

          370
        • Table 9-45. Bit Settings for Register Initialization Data Structure

          370
        • Figure 9-59. PCI Configuration Data Structure for the EEPROM

          371
  • 9.12 Message Unit (I2O)

    371
    • 9.12.1 Message Registers

      371
      • 9.12.1.1 Inbound Message Registers (IMRx)

        372
        • Figure 9-60. Inbound Message Registers (IMRx)

          372
        • Table 9-46. IMRx Field Descriptions

          372
      • 9.12.1.2 Outbound Message Registers (OMRx)

        372
        • Figure 9-61. Outbound Message Registers (OMRx)

          373
        • Table 9-47. OMRx Field Descriptions

          373
    • 9.12.2 Door Bell Registers

      373
      • 9.12.2.1 Outbound Doorbell Register (ODR)

        373
        • Figure 9-62. Outbound Doorbell Register (ODR)

          374
        • Table 9-48. ODR Field Descriptions

          374
      • 9.12.2.2 Inbound Doorbell Register (IDR)

        374
        • Figure 9-63. Inbound Doorbell Register (IDR)

          374
        • Table 9-49. IDR Field Descriptions

          375
    • 9.12.3 I2O Unit

      375
      • Figure 9-64. I2O Message Queue

        376
      • 9.12.3.1 PCI Configuration Identification

        376
      • 9.12.3.2 Inbound FIFOs

        376
        • 9.12.3.2.1 Inbound Free_FIFO Head Pointer Register (IFHPR) and Inbound Free_FIFO Tail Pointer Register (IFTPR)

          377
          • Figure 9-65. Inbound Free_FIFO Head Pointer Register (IFHPR)

            377
          • Table 9-50. IFHPR Field Descriptions

            377
          • Figure 9-66. Inbound Free_FIFO Tail Pointer Register (IFTPR)

            378
          • Table 9-51. IFTPR Field Descriptions

            378
        • 9.12.3.2.2 Inbound Post_FIFO Head Pointer Register (IPHPR) and Inbound Post_FIFO Tail Pointer Register (IPTPR)

          378
          • Figure 9-67. Inbound Post_FIFO Head Pointer Register (IPHPR)

            379
          • Table 9-52. IPHPR Field Descriptions

            379
          • Figure 9-68. Inbound Post_FIFO Tail Pointer Register (IPTPR)

            379
          • Table 9-53. IPTPR Field Descriptions

            380
      • 9.12.3.3 Outbound FIFOs

        380
        • 9.12.3.3.1 Outbound Free_FIFO Head Pointer Register (OFHPR) and Outbound Free_FIFO Tail Pointer Register (OFTPR)

          380
          • Figure 9-69. Outbound Free_FIFO Head Pointer Register (OFHPR)

            380
          • Table 9-54. OFHPR Field Descriptions

            381
          • Figure 9-70. Outbound Free_FIFO Tail Pointer Register (OFTPR)

            381
          • Table 9-55. OFTPR Field Descriptions

            381
        • 9.12.3.3.2 Outbound Post_FIFO Head Pointer Register (OPHPR) and Outbound Post_FIFO Tail Pointer Register (OPTPR)

          381
          • Figure 9-71. Outbound Post_FIFO Head Pointer Register (OPHPR)

            382
          • Table 9-56. OPHPR Field Descriptions

            382
          • Figure 9-72. Outbound Post_FIFO Tail Pointer Register (OPTPR)

            383
          • Table 9-57. OPTPR Field Descriptions

            383
      • 9.12.3.4 I2O Registers

        383
        • 9.12.3.4.1 Inbound FIFO Queue Port Register (IFQPR)

          383
          • Figure 9-73. Inbound FIFO Queue Port Register (IFQPR)

            383
          • Table 9-58. IFQPR Field Descriptions

            384
        • 9.12.3.4.2 Outbound FIFO Queue Port Register (OFQPR)

          384
          • Figure 9-74. Outbound FIFO Queue Port Register (OFQPR)

            384
          • Table 9-59. OFQPR Field Descriptions

            384
        • 9.12.3.4.3 Outbound Message Interrupt Status Register (OMISR)

          384
          • Figure 9-75. Outbound Message Interrupt Status Register (OMISR)

            385
          • Table 9-60. OMISR Field Descriptions

            385
        • 9.12.3.4.4 Outbound Message Interrupt Mask Register (OMIMR)

          385
          • Figure 9-76. Outbound Message Interrupt Mask Register (OMIMR)

            386
          • Table 9-61. OMIMR Field Descriptions

            386
        • 9.12.3.4.5 Inbound Message Interrupt Status Register (IMISR)

          386
          • Figure 9-77. Inbound Message Interrupt Status Register (IMISR)

            387
          • Table 9-62. IMISR Field Descriptions

            387
        • 9.12.3.4.6 Inbound Message Interrupt Mask Register (IMIMR)

          388
          • Figure 9-78. Inbound Message Interrupt Mask Register (IMIMR)

            388
          • Table 9-63. IMIMR Field Descriptions (continued)

            388
        • 9.12.3.4.7 Messaging Unit Control Register (MUCR)

          389
          • Figure 9-79. Messaging Unit Control Register (MUCR)

            389
          • Table 9-64. MUCR Field Descriptions

            389
        • 9.12.3.4.8 Queue Base Address Register (QBAR)

          390
          • Figure 9-80. Queue Base Address Register (QBAR)

            390
          • Table 9-65. QBAR Field Descriptions

            390
  • 9.13 DMA Controller

    391
    • Figure 9-81. DMA Controller Block Diagram

      391
    • 9.13.1 DMA Operation

      391
      • 9.13.1.1 DMA Direct Mode

        392
      • 9.13.1.2 DMA Chaining Mode

        392
      • 9.13.1.3 DMA Coherency

        393
      • 9.13.1.4 Halt and Error Conditions

        393
      • 9.13.1.5 DMA Transfer Types

        393
      • 9.13.1.6 DMA Registers

        394
        • 9.13.1.6.1 DMA Mode Register [0-3] (DMAMRx)

          394
          • Figure 9-82. DMA Mode Register [0-3] (DMAMRx)

            394
          • Table 9-66. DMAMRx Field Descriptions (continued)

            395
        • 9.13.1.6.2 DMA Status Register [0-3] (DMASRx)

          396
          • Figure 9-83. DMA Status Register [0-3] (DMASRx)

            396
          • Table 9-67. DMASRx Field Descriptions

            397
        • 9.13.1.6.3 DMA Current Descriptor Address Register [0-3] (DMACDARx)

          397
          • Figure 9-84. DMA Current Descriptor Address Register [0-3] (DMACDARx)

            397
          • Table 9-68. DMACDARx Field Descriptions

            398
        • 9.13.1.6.4 DMA Source Address Register [0-3] (DMASARx)

          398
          • Figure 9-85. DMA Source Address Register [0-3] (DMASARx)

            398
          • Table 9-69. DMASARx Field Descriptions

            398
        • 9.13.1.6.5 DMA Destination Address Register [0-3] (DMADARx)

          398
          • Figure 9-86. DMA Destination Address Register [0-3] (DMADARx)

            399
          • Table 9-70. DMADARx Field Descriptions

            399
        • 9.13.1.6.6 DMA Byte Count Register [0-3] (DMABCRx)

          399
          • Figure 9-87. DMA Byte Count Register [0-3] (DMABCRx)

            399
          • Table 9-71. DMABCRx Field Descriptions

            400
        • 9.13.1.6.7 DMA Next Descriptor Address Register [0-3] (DMANDARx)

          400
          • Figure 9-88. DMA Next Descriptor Address Register [0-3] (DMANDARx)

            400
          • Table 9-72. DMANDARx Field Descriptions

            400
    • 9.13.2 DMA Segment Descriptors

      401
      • Table 9-73. DMA Segment Descriptor Fields

        401
      • Figure 9-89. DMA Chain of Segment Descriptors

        402
      • 9.13.2.1 Descriptor in Big Endian Mode

        402
      • 9.13.2.2 Descriptor in Little Endian Mode

        403
  • 9.14 Error Handling

    403
    • 9.14.1 Interrupt and Error Signals

      403
      • 9.14.1.1 PCI Bus Error Signals

        403
        • 9.14.1.1.1 System Error (SERR)

          404
        • 9.14.1.1.2 Parity Error (PERR)

          404
        • 9.14.1.1.3 Error Reporting

          404
      • 9.14.1.2 Illegal Register Access Error

        404
      • 9.14.1.3 PCI Interface

        404
        • 9.14.1.3.1 Address Parity Error

          405
        • 9.14.1.3.2 Data Parity Error

          405
        • 9.14.1.3.3 Master-Abort Transaction Termination

          405
        • 9.14.1.3.4 Target-Abort Error

          406
        • 9.14.1.3.5 NMI

          406
      • 9.14.1.4 Embedded Utilities

        406
        • 9.14.1.4.1 Outbound Free Queue Overflow

          406
        • 9.14.1.4.2 Inbound Post Queue Overflow

          406
        • 9.14.1.4.3 Inbound DoorBell Machine Check

          406
• Chapter 10 Clocks and Power Control

  407
  • 10.1 Clock Unit

    407
  • 10.2 Clock Configuration

    407
  • 10.3 External Clock Inputs

    407
  • 10.4 Main PLL

    408
    • 10.4.1 PLL Block Diagram

      408
      • Figure 10-1. System PLL Block Diagram

        408
    • 10.4.2 Skew Elimination

      409
    • 10.4.3 PCI Bridge Clocking

      409
      • 10.4.3.1 PCI Bridge as an Agent Operating from the PCI System Clock

        409
        • Figure 10-2. PCI Bridge as an Agent, Operating from the PCI System Clock

          410
      • 10.4.3.2 PCI Bridge as a Host and Generating the PCI System Clock

        410
        • Figure 10-3. PCI Bridge as a Host, Generating the PCI System Clock

          410
        • 10.4.3.2.1 CPM CLOCK and PCI Frequency Equations

          411
  • 10.5 Clock Dividers

    411
  • 10.6 PowerQUICC II Internal Clock Signals

    411
    • 10.6.1 General System Clocks

      411
  • 10.7 PLL Pins

    412
    • Table 10-1. Dedicated PLL Pins (continued)

      412
    • Figure 10-4. PLL Filtering Circuit

      413
  • 10.8 System Clock Control Register (SCCR)

    414
    • Figure 10-5. System Clock Control Register (SCCR)

      414
    • Table 10-2. SCCR Field Descriptions (continued)

      414
  • 10.9 System Clock Mode Register (SCMR)

    415
    • Figure 10-6. System Clock Mode Register (SCMR)

      415
    • Table 10-3. SCMR Field Descriptions

      416
    • Figure 10-7. Relationships of SCMR Parameters

      416
    • Table 10-4. 60x Bus-to-Core Frequency

      417
  • 10.10 Basic Power Structure

    417
• Chapter 11 Memory Controller

  419
  • Figure 11-1. Dual-Bus Architecture

    420
  • 11.1 Features

    421
  • 11.2 Basic Architecture

    422
    • Figure 11-2. Memory Controller Machine Selection

      423
    • Figure 11-3. Simple System Configuration

      424
    • Figure 11-4. Basic Memory Controller Operation

      425
    • 11.2.1 Address and Address Space Checking

      425
    • 11.2.2 Page Hit Checking

      425
    • 11.2.3 Error Checking and Correction (ECC)

      426
    • 11.2.4 Parity Generation and Checking

      426
    • 11.2.5 Transfer Error Acknowledge (TEA) Generation

      426
    • 11.2.6 Machine Check Interrupt (MCP) Generation

      426
    • 11.2.7 Data Buffer Controls (BCTLx and LWR)

      427
    • 11.2.8 Atomic Bus Operation

      427
    • 11.2.9 Data Pipelining

      427
    • 11.2.10 External Memory Controller Support

      428
    • 11.2.11 External Address Latch Enable Signal (ALE)

      428
    • 11.2.12 ECC/Parity Byte Select (PBSE)

      428
    • 11.2.13 Partial Data Valid Indication (PSDVAL)

      429
      • Table 11-1. Number of PSDVAL Assertions Needed for TA Assertion

        429
      • Figure 11-5. Partial Data Valid for 32-Bit Port Size Memory, Double-Word Transfer

        429
    • 11.2.14 BADDR[27:31] Signal Connections

      430
      • Table 11-2. BADDR Connections

        430
  • 11.3 Register Descriptions

    430
    • Table 11-3. 60x Bus Memory Controller Registers

      430
    • 11.3.1 Base Registers (BRx)

      431
      • Figure 11-6. Base Registers (BRx)

        431
      • Table 11-4. BRx Field Descriptions (continued)

        431
    • 11.3.2 Option Registers (ORx)

      433
      • Figure 11-7. Option Registers (ORx)-SDRAM Mode

        433
      • Table 11-5. ORx Field Descriptions (SDRAM Mode) (continued)

        434
      • Figure 11-8. ORx -GPCM Mode

        435
      • Table 11-6. ORx-GPCM Mode Field Descriptions (continued)

        435
      • Figure 11-9. ORx-UPM Mode

        437
      • Table 11-7. Option Register (ORx)-UPM Mode

        437
    • 11.3.3 60x SDRAM Mode Register (PSDMR)

      438
      • Figure 11-10. 60x/Local SDRAM Mode Register (PSDMR/LSDMR)

        438
      • Table 11-8. PSDMR Field Descriptions (continued)

        439
    • 11.3.4 Local Bus SDRAM Mode Register (LSDMR)

      441
      • Table 11-9. LSDMR Field Descriptions (continued)

        441
    • 11.3.5 Machine A/B/C Mode Registers (MxMR)

      444
      • Figure 11-11. Machine x Mode Registers (MxMR)

        444
      • Table 11-10. Machine x Mode Registers (MxMR) (continued)

        445
    • 11.3.6 Memory Data Register (MDR)

      446
      • Figure 11-12. Memory Data Register (MDR)

        447
      • Table 11-11. MDR Field Descriptions

        447
    • 11.3.7 Memory Address Register (MAR)

      447
      • Figure 11-13. Memory Address Register (MAR)

        447
      • Table 11-12. MAR Field Description

        448
    • 11.3.8 60x Bus-Assigned UPM Refresh Timer (PURT)

      448
      • Figure 11-14. 60x Bus-Assigned UPM Refresh Timer (PURT)

        448
      • Table 11-13. 60x Bus-Assigned UPM Refresh Timer (PURT)

        448
    • 11.3.9 Local Bus-Assigned UPM Refresh Timer (LURT)

      448
      • Figure 11-15. Local Bus-Assigned UPM Refresh Timer (LURT)

        448
      • Table 11-14. Local Bus-Assigned UPM Refresh Timer (LURT)

        449
    • 11.3.10 60x Bus-Assigned SDRAM Refresh Timer (PSRT)

      449
      • Figure 11-16. 60x Bus-Assigned SDRAM Refresh Timer (PSRT)

        449
      • Table 11-15. 60x Bus-Assigned SDRAM Refresh Timer (PSRT)

        449
    • 11.3.11 Local Bus-Assigned SDRAM Refresh Timer (LSRT)

      449
      • Figure 11-17. Local Bus-Assigned SDRAM Refresh Timer (LSRT)

        450
      • Table 11-16. LSRT Field Descriptions

        450
    • 11.3.12 Memory Refresh Timer Prescaler Register (MPTPR)

      450
      • Figure 11-18. Memory Refresh Timer Prescaler Register (MPTPR)

        450
      • Table 11-17. MPTPR Field Descriptions

        450
    • 11.3.13 60x Bus Error Status and Control Registers (TESCRx)

      451
    • 11.3.14 Local Bus Error Status and Control Registers (L_TESCRx)

      451
  • 11.4 SDRAM Machine

    451
    • Table 11-18. SDRAM Interface Signals

      451
    • Figure 11-19. 128-Mbyte SDRAM (Eight-Bank Configuration, Banks 1 and 8 Shown)

      452
    • 11.4.1 Supported SDRAM Configurations

      453
    • 11.4.2 SDRAM Power-On Initialization

      453
    • 11.4.3 JEDEC-Standard SDRAM Interface Commands

      453
      • Table 11-19. SDRAM Interface Commands

        454
    • 11.4.4 Page-Mode Support and Pipeline Accesses

      454
    • 11.4.5 Bank Interleaving

      455
      • 11.4.5.1 Using BNKSEL Signals in Single-PowerQUICC II Bus Mode

        455
      • 11.4.5.2 SDRAM Address Multiplexing (SDAM and BSMA)

        455
        • Table 11-20. SDRAM Address Multiplexing (A0-A15)

          456
        • Table 11-21. SDRAM Address Multiplexing (A16-A31)

          456
    • 11.4.6 SDRAM Device-Specific Parameters

      456
      • 11.4.6.1 Precharge-to-Activate Interval

        457
        • Figure 11-20. PRETOACT = 2 (2 Clock Cycles)

          457
      • 11.4.6.2 Activate to Read/Write Interval

        457
        • Figure 11-21. ACTTORW = 2 (2 Clock Cycles)

          458
      • 11.4.6.3 Column Address to First Data Out-CAS Latency

        458
        • Figure 11-22. CL = 2 (2 Clock Cycles)

          458
      • 11.4.6.4 Last Data Out to Precharge

        459
        • Figure 11-23. LDOTOPRE = 2 (-2 Clock Cycles)

          459
      • 11.4.6.5 Last Data In to Precharge-Write Recovery

        459
        • Figure 11-24. WRC = 2 (2 Clock Cycles)

          459
      • 11.4.6.6 Refresh Recovery Interval (RFRC)

        460
        • Figure 11-25. RFRC = 4 (6 Clock Cycles)

          460
      • 11.4.6.7 External Address Multiplexing Signal

        460
        • Figure 11-26. EAMUX = 1

          460
      • 11.4.6.8 External Address and Command Buffers (BUFCMD)

        460
        • Figure 11-27. BUFCMD = 1

          461
    • 11.4.7 SDRAM Interface Timing

      461
      • Figure 11-28. SDRAM Single-Beat Read, Page Closed, CL = 3

        461
      • Figure 11-29. SDRAM Single-Beat Read, Page Hit, CL = 3

        462
      • Figure 11-30. SDRAM Two-Beat Burst Read, Page Closed, CL = 3

        462
      • Figure 11-31. SDRAM Four-Beat Burst Read, Page Miss, CL = 3

        462
      • Figure 11-32. SDRAM Single-Beat Write, Page Hit

        463
      • Figure 11-33. SDRAM Three-Beat Burst Write, Page Closed

        463
      • Figure 11-34. SDRAM Read-after-Read Pipeline, Page Hit, CL = 3

        463
      • Figure 11-35. SDRAM Write-after-Write Pipelined, Page Hit

        464
      • Figure 11-36. SDRAM Read-after-Write Pipelined, Page Hit

        464
    • 11.4.8 SDRAM Read/Write Transactions

      464
    • 11.4.9 SDRAM Mode-Set Command Timing

      465
      • Figure 11-37. SDRAM Mode-Set Command Timing

        465
      • Figure 11-38. Mode Data Bit Settings

        465
    • 11.4.10 SDRAM Refresh

      465
    • 11.4.11 SDRAM Refresh Timing

      466
      • Figure 11-39. SDRAM Bank-Staggered CBR Refresh Timing

        466
    • 11.4.12 SDRAM Configuration Examples

      466
      • 11.4.12.1 SDRAM Configuration Example (Page-Based Interleaving)

        467
        • Table 11-22. 60x Address Bus Partition

          467
        • Table 11-23. SDRAM Device Address Port during activate Command

          467
        • Table 11-24. SDRAM Device Address Port during read/write Command

          467
        • Table 11-25. Register Settings (Page-Based Interleaving)

          468
    • 11.4.13 SDRAM Configuration Example (Bank-Based Interleaving)

      468
      • Table 11-26. 60x Address Bus Partition

        468
      • Table 11-27. SDRAM Device Address Port during activate Command

        469
      • Table 11-28. SDRAM Device Address Port during read/write Command

        469
      • Table 11-29. Register Settings (Bank-Based Interleaving)

        469
  • 11.5 General-Purpose Chip-Select Machine (GPCM)

    469
    • Table 11-30. GPCM Interfaces Signals

      470
    • Figure 11-40. GPCM-to-SRAM Configuration

      470
    • 11.5.1 Timing Configuration

      471
      • Table 11-31. GPCM Strobe Signal Behavior

        471
      • 11.5.1.1 Chip-Select Assertion Timing

        471
        • Figure 11-41. GPCM Peripheral Device Interface

          472
        • Figure 11-42. GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0)

          472
      • 11.5.1.2 Chip-Select and Write Enable Deassertion Timing

        472
        • Figure 11-43. GPCM Memory Device Interface

          473
        • Figure 11-44. GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0)

          473
        • Figure 11-45. GPCM Memory Device Basic Timing (ACS ¹ 00, CSNT = 1, TRLX = 0)

          474
      • 11.5.1.3 Relaxed Timing

        474
        • Figure 11-46. GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1)

          474
        • Figure 11-47. GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0,TRLX = 1)

          475
        • Figure 11-48. GPCM Relaxed-Timing Write (ACS = 10, SCY = 0, CSNT = 1, TRLX = 1)

          475
        • Figure 11-49. GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1)

          476
      • 11.5.1.4 Output Enable (OE) Timing

        476
      • 11.5.1.5 Programmable Wait State Configuration

        476
      • 11.5.1.6 Extended Hold Time on Read Accesses

        477
        • Table 11-32. TRLX and EHTR Combinations

          477
        • Figure 11-50. GPCM Read Followed by Read (ORx[29-30] = 00, Fastest Timing)

          477
        • Figure 11-51. GPCM Read Followed by Read (ORx[29-30] = 01)

          478
        • Figure 11-52. GPCM Read Followed by Write (ORx[29-30] = 01)

          478
        • Figure 11-53. GPCM Read Followed by Write (ORx[29-30] = 10)

          479
    • 11.5.2 External Access Termination

      479
      • Figure 11-54. External Termination of GPCM Access

        480
    • 11.5.3 Boot Chip-Select Operation

      480
      • Table 11-33. . Boot Bank Field Values after Reset (continued)

        480
    • 11.5.4 Differences between MPC8xx’s GPCM and MPC82xx’s GPCM

      481
  • 11.6 User-Programmable Machines (UPMs)

    481
    • Table 11-34. UPM Interfaces Signals

      481
    • Figure 11-55. User-Programmable Machine Block Diagram

      482
    • 11.6.1 Requests

      482
      • Figure 11-56. RAM Array Indexing

        483
      • Table 11-35. UPM Routines Start Addresses

        483
      • 11.6.1.1 Memory Access Requests

        484
      • 11.6.1.2 UPM Refresh Timer Requests

        484
        • Figure 11-57. Memory Refresh Timer Request Block Diagram

          484
      • 11.6.1.3 Software Requests-run Command

        485
      • 11.6.1.4 Exception Requests

        485
    • 11.6.2 Programming the UPMs

      485
    • 11.6.3 Clock Timing

      485
      • Figure 11-58. Memory Controller UPM Clock Scheme for Integer Clock Ratios

        486
      • Figure 11-59. Memory Controller UPM Clock Scheme for Non-Integer (2.5:1/3.5:1) Clock Ratios

        486
      • Figure 11-60. UPM Signals Timing Example

        487
    • 11.6.4 The RAM Array

      487
      • Figure 11-61. RAM Array and Signal Generation

        488
      • 11.6.4.1 RAM Words

        488
        • Figure 11-62. The RAM Word

          488
        • Table 11-36. RAM Word Bit Settings (continued)

          489
        • 11.6.4.1.1 Chip-Select Signals (CxTx)

          492
          • Figure 11-63. CS Signal Selection

            493
        • 11.6.4.1.2 Byte-Select Signals (BxTx)

          493
          • Figure 11-64. BS Signal Selection

            493
        • 11.6.4.1.3 General-Purpose Signals (GxTx, GOx)

          494
        • 11.6.4.1.4 Loop Control

          494
          • Table 11-37. MxMR Loop Field Usage

            494
        • 11.6.4.1.5 Repeat Execution of Current RAM Word (REDO)

          494
      • 11.6.4.2 Address Multiplexing

        495
        • Table 11-38. UPM Address Multiplexing

          495
      • 11.6.4.3 Data Valid and Data Sample Control

        495
        • Figure 11-65. UPM Read Access Data Sampling

          496
      • 11.6.4.4 Signals Negation

        496
      • 11.6.4.5 The Wait Mechanism

        496
        • Figure 11-66. Wait Mechanism Timing for Internal and External Synchronous Masters

          497
      • 11.6.4.6 Extended Hold Time on Read Accesses

        497
    • 11.6.5 UPM DRAM Configuration Example

      497
      • Table 11-39. 60x Address Bus Partition

        498
      • Table 11-40. DRAM Device Address Port during an activate command

        498
      • Table 11-41. Register Settings

        498
    • 11.6.6 Differences between MPC8xx UPM and MPC82xx UPM

      498
  • 11.7 Memory System Interface Example Using UPM

    499
    • Figure 11-67. DRAM Interface Connection to the 60x Bus (64-Bit Port Size)

      499
    • Table 11-42. UPMs Attributes Example

      500
    • Figure 11-68. Single-Beat Read Access to FPM DRAM

      501
    • Figure 11-69. Single-Beat Write Access to FPM DRAM

      502
    • Figure 11-70. Burst Read Access to FPM DRAM (No LOOP)

      503
    • Figure 11-71. Burst Read Access to FPM DRAM (LOOP)

      504
    • Figure 11-72. Burst Write Access to FPM DRAM (No LOOP)

      505
    • Figure 11-73. Refresh Cycle (CBR) to FPM DRAM

      506
    • Figure 11-74. Exception Cycle

      507
    • Table 11-43. UPMs Attributes Example

      507
    • Figure 11-75. FPM DRAM Burst Read Access (Data Sampling on Falling Edge of CLKIN)

      509
    • 11.7.0.1 EDO Interface Example

      510
      • Figure 11-76. PowerQUICC II/EDO Interface Connection to the 60x Bus

        510
      • Table 11-44. EDO Connection Field Value Example (continued)

        510
      • Figure 11-77. Single-Beat Read Access to EDO DRAM

        512
      • Figure 11-78. Single-Beat Write Access to EDO DRAM

        513
      • Figure 11-79. Single-Beat Write Access to EDO DRAM Using REDO to Insert Three Wait States

        514
      • Figure 11-80. Burst Read Access to EDO DRAM

        515
      • Figure 11-81. Burst Write Access to EDO DRAM

        516
      • Figure 11-82. Refresh Cycle (CBR) to EDO DRAM

        517
      • Figure 11-83. Exception Cycle For EDO DRAM

        518
  • 11.8 Handling Devices with Slow or Variable Access Times

    519
    • 11.8.1 Hierarchical Bus Interface Example

      519
    • 11.8.2 Slow Devices Example

      519
  • 11.9 External Master Support (60x-Compatible Mode)

    519
    • 11.9.1 60x-Compatible External Masters (non-PowerQUICC II)

      520
    • 11.9.2 PowerQUICC II External Masters

      520
    • 11.9.3 Extended Controls in 60x-Compatible Mode

      520
    • 11.9.4 Address Incrementing for External Bursting Masters

      520
    • 11.9.5 External Masters Timing

      521
      • Figure 11-84. Pipelined Bus Operation and Memory Access in 60x-Compatible Mode

        522
      • Figure 11-85. External Master Access (GPCM)

        523
      • 11.9.5.1 Example of External Master Using the SDRAM Machine

        523
        • Figure 11-86. External Master Configuration with SDRAM Device

          524
• Chapter 12 Secondary (L2) Cache Support

  525
  • 12.1 L2 Cache Configurations

    525
    • 12.1.1 Copy-Back Mode

      525
      • Figure 12-1. L2 Cache in Copy-Back Mode

        526
    • 12.1.2 Write-Through Mode

      526
      • Figure 12-2. External L2 Cache in Write-Through Mode

        528
    • 12.1.3 ECC/Parity Mode

      528
      • Figure 12-3. External L2 Cache in ECC/Parity Mode

        530
  • 12.2 L2 Cache Interface Parameters

    530
  • 12.3 System Requirements When Using the L2 Cache Interface

    531
  • 12.4 L2 Cache Operation

    531
  • 12.5 Timing Example

    531
    • Figure 12-4. Read Access with L2 Cache

      532
• Chapter 13 IEEE 1149.1 Test Access Port

  533
  • 13.1 Overview

    533
    • Figure 13-1. Test Logic Block Diagram

      534
    • Table 13-1. TAP Signals

      534
  • 13.2 TAP Controller

    534
    • Figure 13-2. TAP Controller State Machine

      535
  • 13.3 Boundary Scan Register

    535
    • Figure 13-3. Output Pin Cell (O.Pin)

      536
    • Figure 13-4. Observe-Only Input Pin Cell (I.Obs)

      536
    • Figure 13-5. Output Control Cell (IO.CTL)

      537
    • Figure 13-6. General Arrangement of Bidirectional Pin Cells

      537
  • 13.4 Instruction Register

    537
    • Table 13-2. Instruction Decoding (continued)

      538
  • 13.5 PowerQUICC II Restrictions

    539
  • 13.6 Nonscan Chain Operation

    539
• Part IV Communications Processor Module

  541
  • Intended Audience

    541
  • Contents

    541
  • Suggested Reading

    543
  • Architecture Documentation

    543
  • Conventions

    543
  • Acronyms and Abbreviations

    544
• Chapter 14 Communications Processor Module Overview

  549
  • 14.1 Features

    549
    • Figure 14-1. PowerQUICC II CPM Block Diagram

      551
  • 14.2 PowerQUICC II Serial Configurations

    551
    • Table 14-1. Possible PowerQUICC II Applications

      552
  • 14.3 Communications Processor (CP)

    552
    • 14.3.1 CPM Performance Evaluation

      552
    • 14.3.2 Features

      552
    • 14.3.3 CP Block Diagram

      553
      • Figure 14-2. Communications Processor (CP) Block Diagram

        554
    • 14.3.4 G2 Core Interface

      554
    • 14.3.5 Peripheral Interface

      555
      • Table 14-2. Peripheral Prioritization (continued)

        555
    • 14.3.6 Execution from RAM

      556
    • 14.3.7 RISC Controller Configuration Register (RCCR)

      556
      • Figure 14-3. RISC Controller Configuration Register (RCCR

        557
      • Table 14-3. RISC Controller Configuration Register Field Descriptions (continued)

        557
    • 14.3.8 RISC Time-Stamp Control Register (RTSCR)

      559
      • Figure 14-4. RISC Time-Stamp Control Register (RTSCR)

        559
      • Table 14-4. RTSCR Field Descriptions

        559
    • 14.3.9 RISC Time-Stamp Register (RTSR)

      559
      • Figure 14-5. RISC Time-Stamp Register (RTSR)

        560
    • 14.3.10 RISC Microcode Revision Number

      560
      • Table 14-5. RISC Microcode Revision Number

        560
  • 14.4 Command Set

    560
    • 14.4.1 CP Command Register (CPCR)

      561
      • Figure 14-6. CP Command Register (CPCR)

        561
      • Table 14-6. CP Command Register Field Descriptions (continued)

        561
      • 14.4.1.1 CP Commands

        562
        • Table 14-7. CP Command Opcodes

          563
        • Table 14-8. Command Descriptions (continued)

          564
    • 14.4.2 Command Register Example

      565
    • 14.4.3 Command Execution Latency

      565
  • 14.5 Dual-Port RAM

    565
    • Figure 14-7. Dual-Port RAM Block Diagram

      566
    • Figure 14-8. Dual-Port RAM Memory Map

      567
    • 14.5.1 Buffer Descriptors (BDs)

      568
      • Table 14-9. Buffer Descriptor Format

        568
    • 14.5.2 Parameter RAM

      568
      • Table 14-10. Parameter RAM

        569
  • 14.6 RISC Timer Tables

    570
    • 14.6.1 RISC Timer Table Parameter RAM

      570
      • Figure 14-9. RISC Timer Table RAM Usage

        571
      • Table 14-11. RISC Timer Table Parameter RAM

        571
    • 14.6.2 RISC Timer Command Register (TM_CMD)

      572
      • Figure 14-10. RISC Timer Command Register (TM_CMD)

        572
      • Table 14-12. TM_CMD Field Descriptions

        572
    • 14.6.3 RISC Timer Table Entries

      572
    • 14.6.4 RISC Timer Event Register (RTER)/Mask Register (RTMR)

      572
      • Figure 14-11. RISC Timer Event Register (RTER)/Mask Register (RTMR)

        573
    • 14.6.5 set timer Command

      573
    • 14.6.6 RISC Timer Initialization Sequence

      573
    • 14.6.7 RISC Timer Initialization Example

      574
    • 14.6.8 RISC Timer Interrupt Handling

      574
    • 14.6.9 RISC Timer Table Scan Algorithm

      574
    • 14.6.10 Using the RISC Timers to Track CP Loading

      575
• Chapter 15 Serial Interface with Time-Slot Assigner

  577
  • Figure 15-1. SI Block Diagram

    578
  • 15.1 Features

    579
  • 15.2 Overview

    580
    • Figure 15-2. Various Configurations of a Single TDM Channel

      581
    • Figure 15-3. Dual TDM Channel Example

      582
  • 15.3 Enabling Connections to TSA

    583
    • Figure 15-4. Enabling Connections to the TSA

      584
  • 15.4 Serial Interface RAM

    584
    • 15.4.1 One Multiplexed Channel with Static Frames

      585
      • Figure 15-5. One TDM Channel with Static Frames and Independent Rx and Tx Routes

        585
    • 15.4.2 One Multiplexed Channel with Dynamic Frames

      585
      • Figure 15-6. One TDM Channel with Shadow RAM for Dynamic Route Change

        586
    • 15.4.3 Programming SIx RAM Entries

      586
      • Figure 15-7. SIx RAM Entry Fields

        586
      • Table 15-1. SIx RAM Entry (MCC = 0) (continued)

        587
      • Figure 15-8. Using the SWTR Feature

        588
      • Table 15-2. SIx RAM Entry (MCC = 1)

        589
    • 15.4.4 SIx RAM Programming Example

      590
      • Table 15-3. SIx RAM Entry Descriptions

        590
    • 15.4.5 Static and Dynamic Routing

      590
      • Figure 15-9. Example: SIx RAM Dynamic Changes, TDMa and b, Same SIx RAM Size

        592
  • 15.5 Serial Interface Registers

    593
    • 15.5.1 SI Global Mode Registers (SIxGMR)

      593
      • Figure 15-10. SI Global Mode Registers (SIxGMR)

        593
      • Table 15-4. SIxGMR Field Descriptions

        593
    • 15.5.2 SI Mode Registers (SIxMR)

      593
      • Figure 15-11. SI Mode Registers (SIxMR)

        594
      • Table 15-5. SIxMR Field Descriptions (continued)

        594
      • Figure 15-12. One-Clock Delay from Sync to Data (xFSD = 01)

        596
      • Figure 15-13. No Delay from Sync to Data (xFSD = 00)

        596
      • Figure 15-14. Falling Edge (FE) Effect When CE = 1 and xFSD = 01

        597
      • Figure 15-15. Falling Edge (FE) Effect When CE = 0 and xFSD = 01

        597
      • Figure 15-16. Falling Edge (FE) Effect When CE = 1 and xFSD = 00

        598
      • Figure 15-17. Falling Edge (FE) Effect When CE = 0 and xFSD = 00

        599
    • 15.5.3 SIx RAM Shadow Address Registers (SIxRSR)

      599
      • Figure 15-18. SIx RAM Shadow Address Registers (SIxRSR)

        600
      • Table 15-6. SIxRSR Field Descriptions

        600
    • 15.5.4 SI Command Register (SIxCMDR)

      600
      • Figure 15-19. SI Command Register (SIxCMDR)

        600
      • Table 15-7. SIxCMDR Field Description

        601
    • 15.5.5 SI Status Registers (SIxSTR)

      601
      • Figure 15-20. SI Status Registers (SIxSTR)

        601
      • Table 15-8. SIxSTR Field Descriptions

        601
  • 15.6 Serial Interface IDL Interface Support

    601
    • Figure 15-21. Dual IDL Bus Application Example

      602
    • 15.6.1 IDL Interface Example

      602
      • Figure 15-22. IDL Terminal Adaptor

        603
      • Table 15-9. IDL Signal Descriptions

        603
      • Figure 15-23. IDL Bus Signals

        604
    • 15.6.2 IDL Interface Programming

      605
      • Table 15-10. SIx RAM Entries for an IDL Interface (continued)

        605
  • 15.7 Serial Interface GCI Support

    606
    • Table 15-11. GCI Signals

      607
    • Figure 15-24. GCI Bus Signals

      607
    • 15.7.1 SI GCI Activation/Deactivation Procedure

      608
    • 15.7.2 Serial Interface GCI Programming

      608
      • 15.7.2.1 Normal Mode GCI Programming

        608
      • 15.7.2.2 SCIT Programming

        609
        • Table 15-12. SIx RAM Entries for a GCI Interface (SCIT Mode)

          609
• Chapter 16 CPM Multiplexing

  611
  • Figure 16-1. CPM Multiplexing Logic (CMX) Block Diagram

    612
  • 16.1 Features

    612
  • 16.2 Enabling Connections to TSA or NMSI

    613
    • Figure 16-2. Enabling Connections to the TSA

      614
  • 16.3 NMSI Configuration

    614
    • Figure 16-3. Bank of Clocks

      615
    • Table 16-1. Clock Source Options

      616
  • 16.4 CMX Registers

    617
    • 16.4.1 CMX UTOPIA Address Register (CMXUAR)

      617
      • Figure 16-4. CMX UTOPIA Address Register (CMXUAR)

        617
      • Table 16-2. CMXUAR Field Descriptions (continued)

        617
      • Figure 16-5. Connection of the Master Address

        619
      • Figure 16-6. Connection of the Slave Address

        619
      • Figure 16-7. Multi-PHY Receive Address Multiplexing

        621
    • 16.4.2 CMX SI1 Clock Route Register (CMXSI1CR)

      622
      • Figure 16-8. CMX SI1 Clock Route Register (CMXSI1CR)

        622
      • Table 16-3. CMXSI1CR Field Descriptions

        622
    • 16.4.3 CMX SI2 Clock Route Register (CMXSI2CR)

      622
      • Figure 16-9. CMX SI2 Clock Route Register (CMXSI2CR)

        623
      • Table 16-4. CMXSI2CR Field Descriptions

        623
    • 16.4.4 CMX FCC Clock Route Register (CMXFCR)

      623
      • Figure 16-10. CMX FCC Clock Route Register (CMXFCR)

        624
      • Table 16-5. CMXFCR Field Descriptions (continued)

        624
    • 16.4.5 CMX SCC Clock Route Register (CMXSCR)

      626
      • Figure 16-11. CMX SCC Clock Route Register (CMXSCR)

        626
      • Table 16-6. CMXSCR Field Descriptions (continued)

        626
    • 16.4.6 CMX SMC Clock Route Register (CMXSMR)

      629
      • Figure 16-12. CMX SMC Clock Route Register (CMXSMR)

        629
      • Table 16-7. CMXSMR Field Descriptions

        629
• Chapter 17 Baud-Rate Generators (BRGs)

  631
  • Figure 17-1. Baud-Rate Generator (BRG) Block Diagram

    631
  • 17.1 BRG Configuration Registers 1-8 (BRGCx)

    632
    • Figure 17-2. Baud-Rate Generator Configuration Registers (BRGCx)

      632
    • Table 17-1. BRGCx Field Descriptions

      633
    • Table 17-2. BRG External Clock Source Options

      634
  • 17.2 Autobaud Operation on a UART

    634
  • 17.3 UART Baud Rate Examples

    635
    • Table 17-3. Typical Baud Rates for Asynchronous Communication

      635
• Chapter 18 Timers

  637
  • Figure 18-1. Timer Block Diagram

    637
  • 18.1 Features

    637
  • 18.2 General-Purpose Timer Units

    638
    • 18.2.1 Cascaded Mode

      639
      • Figure 18-2. Timer Cascaded Mode Block Diagram

        639
    • 18.2.2 Timer Global Configuration Registers (TGCR1 and TGCR2)

      639
      • Figure 18-3. Timer Global Configuration Register 1 (TGCR1)

        640
      • Table 18-1. TGCR1 Field Descriptions

        640
      • Figure 18-4. Timer Global Configuration Register 2 (TGCR2)

        641
      • Table 18-2. TGCR2 Field Descriptions

        641
    • 18.2.3 Timer Mode Registers (TMR1-TMR4)

      641
      • Figure 18-5. Timer Mode Registers (TMR1-TMR4)

        642
      • Table 18-3. TMR1-TMR4 Field Descriptions

        642
    • 18.2.4 Timer Reference Registers (TRR1-TRR4)

      642
      • Figure 18-6. Timer Reference Registers (TRR1-TRR4)

        643
    • 18.2.5 Timer Capture Registers (TCR1-TCR4)

      643
      • Figure 18-7. Timer Capture Registers (TCR1-TCR4)

        643
    • 18.2.6 Timer Counters (TCN1-TCN4)

      643
      • Figure 18-8. Timer Counter Registers (TCN1-TCN4)

        643
    • 18.2.7 Timer Event Registers (TER1-TER4)

      643
      • Figure 18-9. Timer Event Registers (TER1-TER4)

        644
      • Table 18-4. TER Field Descriptions

        644
• Chapter 19 SDMA Channels and IDMA Emulation

  645
  • Figure 19-1. SDMA Data Paths

    645
  • 19.1 SDMA Bus Arbitration and Bus Transfers

    646
    • Figure 19-2. SDMA Bus Arbitration (Transaction Steal)

      647
  • 19.2 SDMA Registers

    647
    • 19.2.1 SDMA Status Register (SDSR)

      647
      • Figure 19-3. SDMA Status Register (SDSR)

        647
      • Table 19-1. SDSR Field Descriptions

        647
    • 19.2.2 SDMA Mask Register (SDMR)

      648
    • 19.2.3 SDMA Transfer Error Address Registers (PDTEA and LDTEA)

      648
    • 19.2.4 SDMA Transfer Error MSNUM Registers (PDTEM and LDTEM)

      648
      • Figure 19-4. SDMA Transfer Error MSNUM Registers (PDTEM/LDTEM)

        648
      • Table 19-2. PDTEM and LDTEM Field Descriptions

        648
  • 19.3 IDMA Emulation

    649
  • 19.4 IDMA Features

    649
  • 19.5 IDMA Transfers

    650
    • 19.5.1 Memory-to-Memory Transfers

      650
      • Table 19-3. IDMA Transfer Parameters (continued)

        650
      • Figure 19-5. IDMA Transfer Buffer in the Dual-Port RAM

        651
      • Figure 19-6. Example IDMA Transfer Buffer States for a Memory-to-Memory Transfer (Size = 128 Bytes)

        652
      • 19.5.1.1 External Request Mode

        652
      • 19.5.1.2 Normal Mode

        653
      • 19.5.1.3 Working with a PCI Bus

        653
    • 19.5.2 Memory to/from Peripheral Transfers

      653
      • 19.5.2.1 Dual-Address Transfers

        654
        • 19.5.2.1.1 Peripheral to Memory

          654
        • 19.5.2.1.2 Memory to Peripheral

          654
      • 19.5.2.2 Single Address (Fly-By) Transfers

        654
        • 19.5.2.2.1 Peripheral-to-Memory Fly-By Transfers

          655
        • 19.5.2.2.2 Memory-to-Peripheral Fly-By Transfers

          655
    • 19.5.3 Controlling 60x Bus Bandwidth

      655
    • 19.5.4 PCI Burst Length and Latency Control

      656
  • 19.6 IDMA Priorities

    657
  • 19.7 IDMA Interface Signals

    657
    • 19.7.1 DREQx and DACKx

      657
      • 19.7.1.1 Level-Sensitive Mode

        658
        • Figure 19-7. Timing Requirement for DREQ Negation when IMDA Read from a Peripheral

          659
      • 19.7.1.2 Edge-Sensitive Mode

        659
    • 19.7.2 DONEx

      659
  • 19.8 IDMA Operation

    660
    • 19.8.1 Auto Buffer and Buffer Chaining

      660
      • Figure 19-8. IDMAx Channel’s BD Table

        661
    • 19.8.2 IDMAx Parameter RAM

      661
      • Table 19-4. IDMAx Parameter RAM (continued)

        662
      • 19.8.2.1 DMA Channel Mode (DCM)

        663
        • Figure 19-9. DCM Parameters

          663
        • Table 19-5. DCM Field Descriptions (continued)

          664
      • 19.8.2.2 Data Transfer Types as Programmed in DCM

        665
        • Table 19-6. IDMA Channel Data Transfer Operation (continued)

          665
      • 19.8.2.3 Programming DTS and STS

        666
        • Table 19-7. Valid Memory-to-Memory STS/DTS Values

          666
        • Table 19-8. Valid STS/DTS Values for Peripherals

          667
    • 19.8.3 IDMA Performance

      667
    • 19.8.4 IDMA Event Register (IDSR) and Mask Register (IDMR)

      668
      • Figure 19-10. IDMA Event/Mask Registers (IDSR/IDMR)

        668
      • Table 19-9. IDSR/IDMR Field Descriptions

        668
    • 19.8.5 IDMA BDs

      668
      • Figure 19-11. IDMA BD Structure

        669
      • Table 19-10. IDMA BD Field Descriptions (continued)

        669
  • 19.9 IDMA Commands

    671
    • 19.9.1 start_idma Command

      671
    • 19.9.2 stop_idma Command

      672
  • 19.10 IDMA Bus Exceptions

    672
    • Table 19-11. IDMA Bus Exceptions

      672
    • 19.10.1 Externally Recognizing IDMA Operand Transfers

      673
  • 19.11 Programming the Parallel I/O Registers

    673
    • Table 19-12. Parallel I/O Register Programming-Port C

      673
    • Table 19-13. Parallel I/O Register Programming-Port A

      674
    • Table 19-14. Parallel I/O Register Programming-Port D

      674
  • 19.12 IDMA Programming Examples

    674
    • 19.12.1 Peripheral-to-Memory Mode (60x Bus to Local Bus)-IDMA2

      674
      • Table 19-15. Example: Peripheral-to-Memory Mode-IDMA2 (continued)

        674
    • 19.12.2 Memory-to-Peripheral Fly-By Mode-IDMA3

      676
      • Table 19-16. Example: Memory-to-Peripheral Fly-By Mode (on 60x)-IDMA3 (continued)

        676
    • 19.12.3 Memory-to-Memory (PCI Bus to 60x Bus)-IDMA1

      677
      • Table 19-17. Programming Example: Memory-to-Memory (PCI-to-60x)-IDMA1 (continued)

        677
• Chapter 20 Serial Communications Controllers (SCCs)

  679
  • Figure 20-1. SCC Block Diagram

    680
  • 20.1 Features

    680
    • 20.1.1 The General SCC Mode Registers (GSMR1-GSMR4)

      681
      • Figure 20-2. GSMR_H-General SCC Mode Register (High Order)

        681
      • Table 20-1. GSMR_H Field Descriptions (continued)

        681
      • Figure 20-3. GSMR_L-General SCC Mode Register (Low Order)

        683
      • Table 20-2. GSMR_L Field Descriptions (continued)

        683
    • 20.1.2 Protocol-Specific Mode Register (PSMR)

      687
    • 20.1.3 Data Synchronization Register (DSR)

      687
      • Figure 20-4. Data Synchronization Register (DSR)

        687
    • 20.1.4 Transmit-on-Demand Register (TODR)

      688
      • Figure 20-5. Transmit-on-Demand Register (TODR)

        688
      • Table 20-3. TODR Field Descriptions

        688
  • 20.2 SCC Buffer Descriptors (BDs)

    688
    • Figure 20-6. SCC Buffer Descriptors (BDs)

      689
    • Figure 20-7. SCC BD and Buffer Memory Structure

      690
  • 20.3 SCC Parameter RAM

    691
    • Table 20-4. SCC Parameter RAM Map for All Protocols (continued)

      691
    • 20.3.1 SCC Base Addresses

      692
      • Table 20-5. Parameter RAM-SCC Base Addresses

        693
    • 20.3.2 Function Code Registers (RFCR and TFCR)

      693
      • Figure 20-8. Function Code Registers (RFCR and TFCR)

        693
      • Table 20-6. RFCRx /TFCRx Field Descriptions

        693
    • 20.3.3 Handling SCC Interrupts

      694
      • Table 20-7. SCCx Event, Mask, and Status Registers

        694
    • 20.3.4 Initializing the SCCs

      695
    • 20.3.5 Controlling SCC Timing with RTS, CTS, and CD

      695
      • 20.3.5.1 Synchronous Protocols

        695
        • Figure 20-9. Output Delay from RTS Asserted for Synchronous Protocols

          696
        • Figure 20-10. Output Delay from CTS Asserted for Synchronous Protocols

          696
        • Figure 20-11. CTS Lost in Synchronous Protocols

          697
        • Figure 20-12. Using CD to Control Synchronous Protocol Reception

          698
      • 20.3.5.2 Asynchronous Protocols

        698
    • 20.3.6 Digital Phase-Locked Loop (DPLL) Operation

      699
      • Figure 20-13. DPLL Receiver Block Diagram

        699
      • Figure 20-14. DPLL Transmitter Block Diagram

        700
      • Table 20-8. Preamble Requirements (continued)

        700
      • 20.3.6.1 Encoding Data with a DPLL

        701
        • Figure 20-15. DPLL Encoding Examples

          701
        • Table 20-9. DPLL Codings

          702
    • 20.3.7 Reconfiguring the SCCs

      702
      • 20.3.7.1 General Reconfiguration Sequence for an SCC Transmitter

        702
      • 20.3.7.2 Reset Sequence for an SCC Transmitter

        703
      • 20.3.7.3 General Reconfiguration Sequence for an SCC Receiver

        703
      • 20.3.7.4 Reset Sequence for an SCC Receiver

        703
      • 20.3.7.5 Switching Protocols

        703
    • 20.3.8 Saving Power

      703
• Chapter 21 SCC UART Mode

  705
  • Figure 21-1. UART Character Format

    705
  • 21.1 Features

    706
  • 21.2 Normal Asynchronous Mode

    706
  • 21.3 Synchronous Mode

    707
  • 21.4 SCC UART Parameter RAM

    707
    • Table 21-1. UART-Specific SCC Parameter RAM Memory Map (continued)

      708
  • 21.5 Data-Handling Methods: Character- or Message-Based

    709
  • 21.6 Error and Status Reporting

    709
  • 21.7 SCC UART Commands

    710
    • Table 21-2. Transmit Commands

      710
    • Table 21-3. Receive Commands

      710
  • 21.8 Multidrop Systems and Address Recognition

    710
    • Figure 21-2. Two UART Multidrop Configurations

      711
  • 21.9 Receiving Control Characters

    711
    • Figure 21-3. Control Character Table

      712
    • Table 21-4. Control Character Table, RCCM, and RCCR Descriptions

      712
  • 21.10 Hunt Mode (Receiver)

    713
  • 21.11 Inserting Control Characters into the Transmit Data Stream

    713
    • Figure 21-4. Transmit Out-of-Sequence Register (TOSEQ)

      713
    • Table 21-5. TOSEQ Field Descriptions (continued)

      713
  • 21.12 Sending a Break (Transmitter)

    714
  • 21.13 Sending a Preamble (Transmitter)

    714
  • 21.14 Fractional Stop Bits (Transmitter)

    714
    • Figure 21-5. Asynchronous UART Transmitter

      714
    • Table 21-6. DSR Fields Descriptions

      715
  • 21.15 Handling Errors in the SCC UART Controller

    715
    • Table 21-7. Transmission Errors

      715
    • Table 21-8. Reception Errors

      716
  • 21.16 UART Mode Register (PSMR)

    716
    • Figure 21-6. Protocol-Specific Mode Register for UART (PSMR)

      717
    • Table 21-9. PSMR UART Field Descriptions (continued)

      717
  • 21.17 SCC UART Receive Buffer Descriptor (RxBD)

    718
    • Figure 21-7. SCC UART Receiving using RxBDs

      720
    • Figure 21-8. SCC UART Receive Buffer Descriptor (RxBD)

      721
    • Table 21-10. SCC UART RxBD Status and Control Field Descriptions (continued)

      721
  • 21.18 SCC UART Transmit Buffer Descriptor (TxBD)

    722
    • Figure 21-9. SCC UART Transmit Buffer Descriptor (TxBD)

      722
    • Table 21-11. SCC UART TxBD Status and Control Field Descriptions (continued)

      722
  • 21.19 SCC UART Event Register (SCCE) and Mask Register (SCCM)

    723
    • Figure 21-10. SCC UART Interrupt Event Example

      724
    • Figure 21-11. SCC UART Event Register (SCCE) and Mask Register (SCCM)

      724
    • Table 21-12. SCCE/SCCM Field Descriptions for UART Mode

      725
  • 21.20 SCC UART Status Register (SCCS)

    725
    • Figure 21-12. SCC Status Register for UART Mode (SCCS)

      725
    • Table 21-13. UART SCCS Field Descriptions

      726
  • 21.21 SCC UART Programming Example

    726
  • 21.22 S-Records Loader Application

    727
    • Table 21-14. UART Control Characters for S-Records Example (continued)

      727
• Chapter 22 SCC HDLC Mode

  729
  • 22.1 SCC HDLC Features

    729
  • 22.2 SCC HDLC Channel Frame Transmission

    730
    • Figure 22-1. HDLC Framing Structure

      730
  • 22.3 SCC HDLC Channel Frame Reception

    730
  • 22.4 SCC HDLC Parameter RAM

    731
    • Table 22-1. HDLC-Specific SCC Parameter RAM Memory Map (continued)

      731
    • Figure 22-2. HDLC Address Recognition

      732
  • 22.5 Programming the SCC in HDLC Mode

    732
  • 22.6 SCC HDLC Commands

    733
    • Table 22-2. Transmit Commands

      733
    • Table 22-3. Receive Commands

      733
  • 22.7 Handling Errors in the SCC HDLC Controller

    733
    • Table 22-4. Transmit Errors

      734
    • Table 22-5. Receive Errors

      734
  • 22.8 HDLC Mode Register (PSMR)

    735
    • Figure 22-3. HDLC Mode Register (PSMR)

      735
    • Table 22-6. PSMR HDLC Field Descriptions (continued)

      735
  • 22.9 SCC HDLC Receive Buffer Descriptor (RxBD)

    736
    • Figure 22-4. SCC HDLC Receive Buffer Descriptor (RxBD)

      736
    • Table 22-7. SCC HDLC RxBD Status and Control Field Descriptions (continued)

      736
    • Figure 22-5. SCC HDLC Receiving Using RxBDs

      738
  • 22.10 SCC HDLC Transmit Buffer Descriptor (TxBD)

    739
    • Figure 22-6. SCC HDLC Transmit Buffer Descriptor (TxBD)

      739
    • Table 22-8. SCC HDLC TxBD Status and Control Field Descriptions

      739
  • 22.11 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)

    740
    • Figure 22-7. HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)

      740
    • Table 22-9. SCCE/SCCM Field Descriptions (continued)

      740
    • Figure 22-8. SCC HDLC Interrupt Event Example

      741
  • 22.12 SCC HDLC Status Register (SCCS)

    742
    • Figure 22-9. CC HDLC Status Register (SCCS)

      742
    • Table 22-10. HDLC SCCS Field Descriptions

      742
  • 22.13 SCC HDLC Programming Examples

    742
  • 22.14 SCC HDLC Programming Example #1

    742
    • 22.14.1 SCC HDLC Programming Example #2

      744
  • 22.15 HDLC Bus Mode with Collision Detection

    744
    • Figure 22-10. Typical HDLC Bus Multimaster Configuration

      745
    • Figure 22-11. Typical HDLC Bus Single-Master Configuration

      746
    • 22.15.1 HDLC Bus Features

      746
    • 22.15.2 Accessing the HDLC Bus

      746
      • Figure 22-12. Detecting an HDLC Bus Collision

        747
    • 22.15.3 Increasing Performance

      747
      • Figure 22-13. Nonsymmetrical Tx Clock Duty Cycle for Increased Performance

        748
    • 22.15.4 Delayed RTS Mode

      748
      • Figure 22-14. HDLC Bus Transmission Line Configuration

        748
      • Figure 22-15. Delayed RTS Mode

        749
    • 22.15.5 Using the Time-Slot Assigner (TSA)

      749
      • Figure 22-16. HDLC Bus TDM Transmission Line Configuration

        749
    • 22.15.6 HDLC Bus Protocol Programming

      750
      • 22.15.6.1 Programming GSMR and PSMR for the HDLC Bus Protocol

        750
      • 22.15.6.2 HDLC Bus Controller Programming Example

        750
• Chapter 23 SCC BISYNC Mode

  751
  • Figure 23-1. Classes of BISYNC Frames

    751
  • 23.1 Features

    752
  • 23.2 SCC BISYNC Channel Frame Transmission

    752
  • 23.3 SCC BISYNC Channel Frame Reception

    753
  • 23.4 SCC BISYNC Parameter RAM

    753
    • Table 23-1. SCC BISYNC Parameter RAM Memory Map

      753
  • 23.5 SCC BISYNC Commands

    754
    • Table 23-2. Transmit Commands

      755
    • Table 23-3. Receive Commands

      755
  • 23.6 SCC BISYNC Control Character Recognition

    755
    • Figure 23-2. Control Character Table and RCCM

      756
    • Table 23-4. Control Character Table and RCCM Field Descriptions

      757
  • 23.7 BISYNC SYNC Register (BSYNC)

    757
    • Figure 23-3. BISYNC SYNC (BSYNC)

      757
    • Table 23-5. BSYNC Field Descriptions

      758
  • 23.8 SCC BISYNC DLE Register (BDLE)

    758
    • Figure 23-4. BISYNC DLE (BDLE)

      758
    • Table 23-6. BDLE Field Descriptions

      759
  • 23.9 Sending and Receiving the Synchronization Sequence

    759
    • Table 23-7. Receiver SYNC Pattern Lengths of the DSR

      759
  • 23.10 Handling Errors in the SCC BISYNC

    759
    • Table 23-8. Transmit Errors

      760
    • Table 23-9. Receive Errors

      760
  • 23.11 BISYNC Mode Register (PSMR)

    760
    • Figure 23-5. Protocol-Specific Mode Register for BISYNC (PSMR)

      760
    • Table 23-10. PSMR Field Descriptions (continued)

      761
  • 23.12 SCC BISYNC Receive BD (RxBD)

    762
    • Figure 23-6. SCC BISYNC RxBD

      762
    • Table 23-11. SCC BISYNC RxBD Status and Control Field Descriptions (continued)

      762
  • 23.13 SCC BISYNC Transmit BD (TxBD)

    764
    • Figure 23-7. SCC BISYNC Transmit BD (TxBD)

      764
    • Table 23-12. SCC BISYNC TxBD Status and Control Field Descriptions (continued)

      764
  • 23.14 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)

    765
    • Figure 23-8. BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)

      766
    • Table 23-13. SCCE/SCCM Field Descriptions

      766
  • 23.15 SCC Status Registers (SCCS)

    766
    • Figure 23-9. SCC Status Registers (SCCS)

      766
    • Table 23-14. SCCS Field Descriptions

      767
  • 23.16 Programming the SCC BISYNC Controller

    767
    • Table 23-15. Control Characters

      768
  • 23.17 SCC BISYNC Programming Example

    768
• Chapter 24 SCC Transparent Mode

  771
  • 24.1 Features

    771
  • 24.2 SCC Transparent Channel Frame Transmission Process

    772
  • 24.3 SCC Transparent Channel Frame Reception Process

    772
  • 24.4 Achieving Synchronization in Transparent Mode

    773
    • 24.4.1 Synchronization in NMSI Mode

      773
      • 24.4.1.1 In-Line Synchronization Pattern

        773
        • Table 24-1. Receiver SYNC Pattern Lengths of the DSR

          773
      • 24.4.1.2 External Synchronization Signals

        773
        • 24.4.1.2.1 External Synchronization Example

          774
          • Figure 24-1. Sending Transparent Frames between PowerQUICC IIs

            774
      • 24.4.1.3 Transparent Mode without Explicit Synchronization

        775
    • 24.4.2 Synchronization and the TSA

      775
      • 24.4.2.1 Inline Synchronization Pattern

        775
      • 24.4.2.2 Inherent Synchronization

        775
    • 24.4.3 End of Frame Detection

      775
  • 24.5 CRC Calculation in Transparent Mode

    776
  • 24.6 SCC Transparent Parameter RAM

    776
    • Table 24-2. SCC Transparent Parameter RAM Memory Map

      776
  • 24.7 SCC Transparent Commands

    776
    • Table 24-3. Transmit Commands (continued)

      776
    • Table 24-4. Receive Commands

      777
  • 24.8 Handling Errors in the Transparent Controller

    777
    • Table 24-5. Transmit Errors

      777
    • Table 24-6. Receive Errors

      778
  • 24.9 Transparent Mode and the PSMR

    778
  • 24.10 SCC Transparent Receive Buffer Descriptor (RxBD)

    778
    • Figure 24-2. SCC Transparent Receive Buffer Descriptor (RxBD)

      778
    • Table 24-7. SCC Transparent RxBD Status and Control Field Descriptions

      779
  • 24.11 SCC Transparent Transmit Buffer Descriptor (TxBD)

    780
    • Figure 24-3. SCC Transparent Transmit Buffer Descriptor (TxBD)

      780
    • Table 24-8. SCC Transparent TxBD Status and Control Field Descriptions (continued) (continued)

      780
  • 24.12 SCC Transparent Event Register (SCCE)/Mask Register (SCCM)

    781
    • Figure 24-4. SCC Transparent Event Register (SCCE)/Mask Register (SCCM)

      781
    • Table 24-9. SCCE/SCCM Field Descriptions (continued)

      781
  • 24.13 SCC Status Register in Transparent Mode (SCCS)

    782
    • Figure 24-5. SCC Status Register in Transparent Mode (SCCS)

      782
    • Table 24-10. SCCS Field Descriptions

      782
  • 24.14 SCC2 Transparent Programming Example

    782
• Chapter 25 SCC Ethernet Mode

  785
  • Figure 25-1. Ethernet Frame Structure

    785
  • 25.1 Ethernet on the PowerQUICC II

    785
    • Figure 25-2. Ethernet Block Diagram

      786
  • 25.2 Features

    786
  • 25.3 Connecting the PowerQUICC II to Ethernet

    788
    • Figure 25-3. Connecting the PowerQUICC II to Ethernet

      788
  • 25.4 SCC Ethernet Channel Frame Transmission

    789
  • 25.5 SCC Ethernet Channel Frame Reception

    790
  • 25.6 The Content-Addressable Memory (CAM) Interface

    790
  • 25.7 SCC Ethernet Parameter RAM

    791
    • Table 25-1. SCC Ethernet Parameter RAM Memory Map (continued)

      791
  • 25.8 Programming the Ethernet Controller

    793
  • 25.9 SCC Ethernet Commands

    793
    • Table 25-2. Transmit Commands

      794
    • Table 25-3. Receive Commands

      794
  • 25.10 SCC Ethernet Address Recognition

    795
    • Figure 25-4. Ethernet Address Recognition Flowchart

      795
  • 25.11 Hash Table Algorithm

    796
  • 25.12 Interpacket Gap Time

    796
  • 25.13 Handling Collisions

    796
  • 25.14 Internal and External Loopback

    797
  • 25.15 Full-Duplex Ethernet Support

    797
  • 25.16 Handling Errors in the Ethernet Controller

    797
    • Table 25-4. Transmission Errors (continued)

      797
    • Table 25-5. Reception Errors

      798
  • 25.17 Ethernet Mode Register (PSMR)

    798
    • Figure 25-5. Ethernet Mode Register (PSMR)

      798
    • Table 25-6. PSMR Field Descriptions

      799
  • 25.18 SCC Ethernet Receive BD

    800
    • Figure 25-6. SCC Ethernet RxBD

      800
    • Table 25-7. SCC Ethernet RxBD Status and Control Field Descriptions (continued)

      800
    • Figure 25-7. Ethernet Receiving using RxBDs

      802
  • 25.19 SCC Ethernet Transmit Buffer Descriptor

    802
    • Figure 25-8. SCC Ethernet TxBD

      803
    • Table 25-8. SCC Ethernet TxBD Status and Control Field Descriptions (continued)

      803
  • 25.20 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)

    804
    • Figure 25-9. SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)

      804
    • Table 25-9. SCCE/SCCM Field Descriptions (continued)

      804
    • Figure 25-10. Ethernet Interrupt Events Example

      805
  • 25.21 SCC Ethernet Programming Example

    806
• Chapter 26 SCC AppleTalk Mode

  809
  • 26.1 Operating the LocalTalk Bus

    809
    • Figure 26-1. LocalTalk Frame Format

      809
  • 26.2 Features

    810
  • 26.3 Connecting to AppleTalk

    810
    • Figure 26-2. Connecting the PowerQUICC II to LocalTalk

      811
  • 26.4 Programming the SCC in AppleTalk Mode

    811
    • 26.4.1 Programming the GSMR

      811
    • 26.4.2 Programming the PSMR

      812
    • 26.4.3 Programming the TODR

      812
    • 26.4.4 SCC AppleTalk Programming Example

      812
• Chapter 27 Serial Management Controllers (SMCs)

  813
  • Figure 27-1. SMC Block Diagram

    813
  • 27.1 Features

    814
  • 27.2 Common SMC Settings and Configurations

    814
    • 27.2.1 SMC Mode Registers (SMCMR1/SMCMR2)

      814
      • Figure 27-2. SMC Mode Registers (SMCMR1/SMCMR2)

        815
      • Table 27-1. SMCMR1/SMCMR2 Field Descriptions (continued)

        815
    • 27.2.2 SMC Buffer Descriptor Operation

      816
      • Figure 27-3. SMC Memory Structure

        817
    • 27.2.3 SMC Parameter RAM

      817
      • Table 27-2. SMC UART and Transparent Parameter RAM Memory Map (continued)

        818
      • 27.2.3.1 SMC Function Code Registers (RFCR/TFCR)

        820
        • Figure 27-4. SMC Function Code Registers (RFCR/TFCR)

          820
        • Table 27-3. RFCR/TFCR Field Descriptions

          820
    • 27.2.4 Disabling SMCs On-the-Fly

      820
      • 27.2.4.1 SMC Transmitter Full Sequence

        821
      • 27.2.4.2 SMC Transmitter Shortcut Sequence

        821
      • 27.2.4.3 SMC Receiver Full Sequence

        821
      • 27.2.4.4 SMC Receiver Shortcut Sequence

        821
      • 27.2.4.5 Switching Protocols

        821
    • 27.2.5 Saving Power

      822
    • 27.2.6 Handling Interrupts in the SMC

      822
  • 27.3 SMC in UART Mode

    822
    • Figure 27-5. SMC UART Frame Format

      822
    • 27.3.1 Features

      823
    • 27.3.2 SMC UART Channel Transmission Process

      823
    • 27.3.3 SMC UART Channel Reception Process

      823
    • 27.3.4 Programming the SMC UART Controller

      823
    • 27.3.5 SMC UART Transmit and Receive Commands

      824
      • Table 27-4. Transmit Commands

        824
      • Table 27-5. Receive Commands

        824
    • 27.3.6 Sending a Break

      824
    • 27.3.7 Sending a Preamble

      825
    • 27.3.8 Handling Errors in the SMC UART Controller

      825
      • Table 27-6. SMC UART Errors

        825
    • 27.3.9 SMC UART RxBD

      825
      • Figure 27-6. SMC UART RxBD

        826
      • Table 27-7. SMC UART RxBD Field Descriptions (continued)

        826
      • Figure 27-7. RxBD Example

        828
    • 27.3.10 SMC UART TxBD

      829
      • Figure 27-8. SMC UART TxBD

        829
      • Table 27-8. SMC UART TxBD Field Descriptions

        829
    • 27.3.11 SMC UART Event Register (SMCE)/Mask Register (SMCM)

      830
      • Figure 27-9. SMC UART Event Register (SMCE)/Mask Register (SMCM)

        830
      • Table 27-9. SMCE/SMCM Field Descriptions

        830
      • Figure 27-10. SMC UART Interrupts Example

        831
    • 27.3.12 SMC UART Controller Programming Example

      831
  • 27.4 SMC in Transparent Mode

    832
    • 27.4.1 Features

      832
    • 27.4.2 SMC Transparent Channel Transmission Process

      833
    • 27.4.3 SMC Transparent Channel Reception Process

      833
    • 27.4.4 Using SMSYN for Synchronization

      834
      • Figure 27-11. Synchronization with SMSYNx

        835
    • 27.4.5 Using the Time-Slot Assigner (TSA) for Synchronization

      835
      • Figure 27-12. Synchronization with the TSA

        836
    • 27.4.6 SMC Transparent Commands

      837
      • Table 27-10. SMC Transparent Transmit Commands

        837
      • Table 27-11. SMC Transparent Receive Commands

        837
    • 27.4.7 Handling Errors in the SMC Transparent Controller

      837
      • Table 27-12. SMC Transparent Error Conditions

        838
    • 27.4.8 SMC Transparent RxBD

      838
      • Figure 27-13. SMC Transparent RxBD

        838
      • Table 27-13. SMC Transparent RxBD Field Descriptions (continued)

        838
    • 27.4.9 SMC Transparent TxBD

      839
      • Table 27-14. SMC Transparent TxBD

        839
      • Table 27-15. SMC Transparent TxBD Field Descriptions

        839
    • 27.4.10 SMC Transparent Event Register (SMCE)/Mask Register (SMCM)

      840
      • Figure 27-14. SMC Transparent Event Register (SMCE)/Mask Register (SMCM)

        841
      • Table 27-16. SMCE/SMCM Field Descriptions

        841
    • 27.4.11 SMC Transparent NMSI Programming Example

      841
  • 27.5 The SMC in GCI Mode

    842
    • 27.5.1 SMC GCI Parameter RAM

      842
      • Table 27-17. SMC GCI Parameter RAM Memory Map

        843
    • 27.5.2 Handling the GCI Monitor Channel

      843
      • 27.5.2.1 SMC GCI Monitor Channel Transmission Process

        843
      • 27.5.2.2 SMC GCI Monitor Channel Reception Process

        843
    • 27.5.3 Handling the GCI C/I Channel

      844
      • 27.5.3.1 SMC GCI C/I Channel Transmission Process

        844
      • 27.5.3.2 SMC GCI C/I Channel Reception Process

        844
    • 27.5.4 SMC GCI Commands

      844
      • Table 27-18. SMC GCI Commands

        844
    • 27.5.5 SMC GCI Monitor Channel RxBD

      844
      • Figure 27-15. SMC Monitor Channel RxBD

        844
      • Table 27-19. SMC Monitor Channel RxBD Field Descriptions

        845
    • 27.5.6 SMC GCI Monitor Channel TxBD

      845
      • Figure 27-16. SMC Monitor Channel TxBD

        845
      • Table 27-20. SMC Monitor Channel TxBD Field Descriptions

        845
    • 27.5.7 SMC GCI C/I Channel RxBD

      845
      • Figure 27-17. SMC C/I Channel RxBD

        846
      • Table 27-21. SMC C/I Channel RxBD Field Descriptions

        846
    • 27.5.8 SMC GCI C/I Channel TxBD

      846
      • Figure 27-18. SMC C/I Channel TxBD

        846
      • Table 27-22. SMC C/I Channel TxBD Field Descriptions

        846
    • 27.5.9 SMC GCI Event Register (SMCE)/Mask Register (SMCM)

      846
      • Figure 27-19. SMC GCI Event Register (SMCE)/Mask Register (SMCM)

        847
      • Table 27-23. SMCE/SMCM Field Descriptions

        847
• Chapter 28 Multi-Channel Controllers (MCCs)

  849
  • 28.1 MCC Operation Overview

    850
    • 28.1.1 MCC Data Structure Organization

      850
      • Figure 28-1. BD Structure for One MCC

        851
  • 28.2 Global MCC Parameters

    852
    • Table 28-1. Global MCC Parameters (continued)

      852
  • 28.3 Channel-Specific Parameters

    853
    • 28.3.1 Channel-Specific HDLC Parameters

      853
      • Table 28-2. Channel-Specific Parameters for HDLC (continued)

        854
      • 28.3.1.1 Internal Transmitter State (TSTATE)-HDLC Mode

        855
        • Figure 28-2. TSTATE High Byte

          855
        • Table 28-3. TSTATE High-Byte Field Descriptions

          855
      • 28.3.1.2 Interrupt Mask (INTMSK)-HDLC Mode

        856
        • Figure 28-3. INTMSK Mask Bits

          856
      • 28.3.1.3 Channel Mode Register (CHAMR)-HDLC Mode

        856
        • Figure 28-4. Channel Mode Register (CHAMR)

          856
        • Table 28-4. CHAMR Field Descriptions (continued)

          857
      • 28.3.1.4 Internal Receiver State (RSTATE)-HDLC Mode

        858
        • Figure 28-5. Rx Internal State (RSTATE) High Byte

          858
        • Table 28-5. RSTATE High-Byte Field Descriptions (continued)

          858
    • 28.3.2 Channel-Specific Transparent Parameters

      859
      • Table 28-6. Channel-Specific Parameters for Transparent Operation (continued)

        859
      • 28.3.2.1 Internal Transmitter State (TSTATE)-Transparent Mode

        860
      • 28.3.2.2 Interrupt Mask (INTMSK)-Transparent Mode

        860
      • 28.3.2.3 Channel Mode Register (CHAMR)-Transparent Mode

        861
        • Figure 28-6. Channel Mode Register (CHAMR)-Transparent Mode

          861
        • Table 28-7. CHAMR Field Descriptions-Transparent Mode (continued)

          861
      • 28.3.2.4 Internal Receiver State (RSTATE)-Transparent Mode

        862
    • 28.3.3 MCC Parameters for AAL1 CES Usage

      862
      • 28.3.3.1 Channel-Specific Parameters-AAL1 CES

        863
        • Table 28-8. CES-Specific Global MCC Parameters

          863
        • 28.3.3.1.1 Interrupt Circular Table Entry and Interrupt Mask (INTMSK)-AAL1 CES

          863
          • Figure 28-7. INTMSK Mask Bits

            863
      • 28.3.3.2 Channel Mode Register (CHAMR)-AAL1 CES

        863
        • Figure 28-8. Channel Mode Register (CHAMR)-CES Mode

          864
        • Table 28-9. CHAMR Field Descriptions-CES Mode (continued)

          864
    • 28.3.4 Channel-Specific SS7 Parameters

      865
      • Table 28-10. Channel-Specific Parameters for SS7 (continued)

        867
      • 28.3.4.1 Extended Channel Mode Register (ECHAMR)-SS7 Mode

        869
        • Figure 28-9. Extended Channel Mode Register (ECHAMR)

          870
        • Table 28-11. ECHAMR Fields Description (continued)

          870
      • 28.3.4.2 Signal Unit Error Monitor (SUERM)-SS7 Mode

        871
        • 28.3.4.2.1 SUERM in Japanese SS7

          871
          • Table 28-12. Parameter Values for SUERM in Japanese SS7

            872
      • 28.3.4.3 SS7 Configuration Register-SS7 Mode

        872
        • Figure 28-10. SS7 Configuration Register (SS7_OPT)

          872
        • Table 28-13. SS7 Configuration Register Fields Description

          872
        • 28.3.4.3.1 AERM Implementation

          873
        • 28.3.4.3.2 AERM in Japanese SS7

          873
        • 28.3.4.3.3 Disabling SUERM

          874
      • 28.3.4.4 SU Filtering-SS7 Mode

        874
        • 28.3.4.4.1 Comparison Mask

          874
          • Figure 28-11. Mask1 Format

            874
          • Figure 28-12. Mask2 Format

            874
        • 28.3.4.4.2 Comparison State Machine

          874
        • 28.3.4.4.3 Filtering Limitations

          875
        • 28.3.4.4.4 Resetting the SU Filtering Mechanism

          875
      • 28.3.4.5 Octet Counting Mode-SS7 Mode

        876
  • 28.4 Channel Extra Parameters

    876
    • Table 28-14. Channel Extra Parameters

      876
  • 28.5 Superchannels

    877
    • 28.5.1 Superchannel Table

      877
      • Figure 28-13. Super Channel Table Entry

        877
    • 28.5.2 Superchannels and Receiving

      878
    • 28.5.3 Transparent Slot Synchronization

      878
    • 28.5.4 Superchannelling Programming Examples

      878
      • Figure 28-14. Transmitter Super Channel Example

        879
      • Figure 28-15. Receiver Super Channel with Slot Synchronization Example

        880
      • Figure 28-16. Receiver Super Channel without Slot Synchronization Example

        881
  • 28.6 MCC Configuration Registers (MCCFx)

    881
    • Figure 28-17. SI MCC Configuration Register (MCCF)

      881
    • Table 28-15. MCCF Field Descriptions

      881
    • Table 28-16. Group Channel Assignments

      882
  • 28.7 MCC Commands

    882
    • Table 28-17. MCC Commands

      883
  • 28.8 MCC Exceptions

    883
    • Figure 28-18. Interrupt Circular Table

      884
    • 28.8.1 MCC Event Register (MCCE)/Mask Register (MCCM)

      885
      • Figure 28-19. MCC Event Register (MCCE)/Mask Register (MCCM)

        885
      • Table 28-18. MCCE/MCCM Register Field Descriptions (continued)

        885
      • 28.8.1.1 Interrupt Circular Table Entry

        886
        • Figure 28-20. Interrupt Circular Table Entry

          886
        • Table 28-19. Interrupt Circular Table Entry Field Descriptions (continued)

          887
      • 28.8.1.2 Global Transmitter Underrun (GUN)

        888
        • 28.8.1.2.1 TDM Clock

          888
        • 28.8.1.2.2 Synchronization Pulse

          888
        • 28.8.1.2.3 SIRAM Programming

          889
        • 28.8.1.2.4 MCC Initialization

          889
        • 28.8.1.2.5 CPM Bandwidth

          889
        • 28.8.1.2.6 CPM Priority

          890
        • 28.8.1.2.7 Bus Latency

          890
      • 28.8.1.3 Recovery from GUN Errors

        890
        • Table 28-20. GUN Error Recovery-.29mm (HiP3) Rev A.1 and B.2 Silicon

          890
        • Table 28-21. GUN Error Recovery-.29mm (HiP3) Rev B.3 and Subsequent Silicon

          891
      • 28.8.1.4 Global Overrun (GOV)

        891
  • 28.9 MCC Buffer Descriptors

    891
    • 28.9.1 Receive Buffer Descriptor (RxBD)

      891
      • Figure 28-21. MCC Receive Buffer Descriptor (RxBD)

        891
      • Table 28-22. RxBD Field Descriptions (continued)

        892
    • 28.9.2 Transmit Buffer Descriptor (TxBD)

      893
      • Figure 28-22. MCC Transmit Buffer Descriptor (TxBD)

        894
      • Table 28-23. TxBD Field Descriptions (continued)

        894
  • 28.10 MCC Initialization and Start/Stop Sequence

    895
    • 28.10.1 Stopping and Restarting a Single-Channel

      896
    • 28.10.2 Stopping and Restarting a Superchannel

      897
  • 28.11 MCC Latency and Performance

    897
• Chapter 29 Fast Communications Controllers (FCCs)

  899
  • 29.1 Overview

    899
    • Figure 29-1. FCC Block Diagram

      901
    • Table 29-1. Internal Clocks to CPM Clock Frequency Ratio

      901
  • 29.2 General FCC Mode Registers (GFMRx)

    901
    • Figure 29-2. General FCC Mode Register (GFMR)

      902
    • Table 29-2. GFMR Register Field Descriptions (continued)

      902
  • 29.3 FCC Protocol-Specific Mode Registers (FPSMRx)

    905
  • 29.4 FCC Data Synchronization Registers (FDSRx)

    906
    • Figure 29-3. FCC Data Synchronization Register (FDSR)

      906
  • 29.5 FCC Transmit-on-Demand Registers (FTODRx)

    906
    • Figure 29-4. FCC Transmit-on-Demand Register (FTODR)

      907
    • Table 29-3. FTODR Field Descriptions

      907
  • 29.6 FCC Buffer Descriptors

    907
    • Figure 29-5. FCC Memory Structure

      908
    • Figure 29-6. Buffer Descriptor Format

      908
  • 29.7 FCC Parameter RAM

    909
    • Table 29-4. FCC Parameter RAM Common to All Protocols except ATM (continued)

      910
    • 29.7.1 FCC Function Code Registers (FCRx)

      911
      • Figure 29-7. Function Code Register (FCRx)

        911
      • Table 29-5. FCRx Field Descriptions

        912
  • 29.8 Interrupts from the FCCs

    912
    • 29.8.1 FCC Event Registers (FCCEx)

      912
    • 29.8.2 FCC Mask Registers (FCCMx)

      913
    • 29.8.3 FCC Status Registers (FCCSx)

      913
  • 29.9 FCC Initialization

    913
  • 29.10 FCC Interrupt Handling

    914
    • 29.10.1 FCC Transmit Errors

      914
      • 29.10.1.1 Re-Initialization Procedure

        914
      • 29.10.1.2 Recovery Sequence

        915
      • 29.10.1.3 Adjusting Transmitter BD Handling

        915
  • 29.11 FCC Timing Control

    915
    • Figure 29-8. Output Delay from RTS Asserted

      916
    • Figure 29-9. Output Delay from CTS Asserted

      916
    • Figure 29-10. CTS Lost

      917
    • Figure 29-11. Using CD to Control Reception

      918
  • 29.12 Disabling the FCCs On-the-Fly

    918
    • 29.12.1 FCC Transmitter Full Sequence

      919
    • 29.12.2 FCC Transmitter Shortcut Sequence

      919
    • 29.12.3 FCC Receiver Full Sequence

      919
    • 29.12.4 FCC Receiver Shortcut Sequence

      919
    • 29.12.5 Switching Protocols

      920
  • 29.13 Saving Power

    920
• Chapter 30 ATM Controller and AAL0, AAL1, and AAL5

  921
  • 30.1 Features

    921
  • 30.2 ATM Controller Overview

    924
    • 30.2.1 Transmitter Overview

      925
      • 30.2.1.1 AAL5 Transmitter Overview

        925
      • 30.2.1.2 AAL1 Transmitter Overview

        925
        • 30.2.1.2.1 AAL1 CES Transmitter Overview

          926
      • 30.2.1.3 AAL0 Transmitter Overview

        926
      • 30.2.1.4 AAL2 Transmitter Overview

        926
      • 30.2.1.5 Transmit External Rate and Internal Rate Modes

        926
    • 30.2.2 Receiver Overview

      926
      • 30.2.2.1 AAL5 Receiver Overview

        927
      • 30.2.2.2 AAL1 Receiver Overview

        927
        • 30.2.2.2.1 AAL1 CES Receiver Overview

          928
      • 30.2.2.3 AAL0 Receiver Overview

        928
      • 30.2.2.4 AAL2 Receiver Overview

        928
    • 30.2.3 Performance Monitoring

      928
    • 30.2.4 ABR Flow Control

      928
  • 30.3 ATM Pace Control (APC) Unit

    928
    • 30.3.1 APC Modes and ATM Service Types

      928
      • Table 30-1. ATM Service Types

        929
    • 30.3.2 APC Unit Scheduling Mechanism

      929
      • Figure 30-1. APC Scheduling Table Mechanism

        929
    • 30.3.3 Determining the Scheduling Table Size

      930
      • 30.3.3.1 Determining the Cells Per Slot (CPS) in a Scheduling Table

        930
      • 30.3.3.2 Determining the Number of Slots in a Scheduling Table

        930
    • 30.3.4 Determining the Time-Slot Scheduling Rate of a Channel

      931
    • 30.3.5 ATM Traffic Type

      931
      • 30.3.5.1 Peak Cell Rate Traffic Type

        931
      • 30.3.5.2 Determining the PCR Traffic Type Parameters

        931
      • 30.3.5.3 Peak and Sustain Traffic Type (VBR)

        932
        • Figure 30-2. VBR Pacing Using the GCRA (Leaky Bucket Algorithm)

          932
        • 30.3.5.3.1 Example for Using VBR Traffic Parameters

          932
        • 30.3.5.3.2 Handling the Cell Loss Priority (CLP)-VBR Type 1 and 2

          933
      • 30.3.5.4 Peak and Minimum Cell Rate Traffic Type (UBR+)

        933
    • 30.3.6 Determining the Priority of an ATM Channel

      933
  • 30.4 VCI/VPI Address Lookup Mechanism

    933
    • 30.4.1 External CAM Lookup

      934
      • Figure 30-3. External CAM Data Input Fields

        934
      • Figure 30-4. External CAM Output Fields

        934
      • Table 30-2. External CAM Input and Output Field Descriptions

        934
    • 30.4.2 Address Compression

      935
      • Figure 30-5. Address Compression Mechanism

        935
      • Table 30-3. Field Descriptions for Address Compression

        936
      • 30.4.2.1 VP-Level Address Compression Table (VPLT)

        936
        • Figure 30-6. General VCOFFSET Formula for Contiguous VCLTs

          936
        • Table 30-4. VCOFFSET Calculation Examples for Contiguous VCLTs

          936
        • Table 30-5. VP-Level Table Entry Address Calculation Example

          937
        • Figure 30-7. VP Pointer Address Compression

          937
      • 30.4.2.2 VC-Level Address Compression Tables (VCLTs)

        937
        • Table 30-6. VC-Level Table Entry Address Calculation Example

          938
        • Figure 30-8. VC Pointer Address Compression

          938
    • 30.4.3 Misinserted Cells

      938
    • 30.4.4 Receive Raw Cell Queue

      938
      • Figure 30-9. ATM Address Recognition Flowchart

        939
  • 30.5 Available Bit Rate (ABR) Flow Control

    939
    • 30.5.1 The ABR Model

      940
      • Figure 30-10. PowerQUICC II’s ABR Basic Model

        940
      • 30.5.1.1 ABR Flow Control Source End-System Behavior

        940
      • 30.5.1.2 ABR Flow Control Destination End-System Behavior

        941
      • 30.5.1.3 ABR Flowcharts

        941
        • Figure 30-11. ABR Transmit Flow

          942
        • Figure 30-12. ABR Transmit Flow (Continued)

          943
        • Figure 30-13. ABR Transmit Flow (Continued)

          944
        • Figure 30-14. ABR Receive Flow

          945
    • 30.5.2 RM Cell Structure

      945
      • Table 30-7. Fields and their Positions in RM Cells

        946
      • 30.5.2.1 RM Cell Rate Representation

        946
        • Figure 30-15. Rate Format for RM Cells

          946
        • Figure 30-16. Rate Formula for RM Cells

          946
    • 30.5.3 ABR Flow Control Setup

      947
  • 30.6 OAM Support

    947
    • 30.6.1 ATM-Layer OAM Definitions

      947
      • Table 30-8. Pre-Assigned Header Values at the UNI

        947
      • Table 30-9. Pre-Assigned Header Values at the NNI

        948
    • 30.6.2 Virtual Path (F4) Flow Mechanism

      948
    • 30.6.3 Virtual Channel (F5) Flow Mechanism

      948
    • 30.6.4 Receiving OAM F4 or F5 Cells

      948
    • 30.6.5 Transmitting OAM F4 or F5 Cells

      948
    • 30.6.6 Performance Monitoring

      949
      • Figure 30-17. Performance Monitoring Cell Structure (FMCs and BRCs)

        949
      • Table 30-10. Performance Monitoring Cell Fields

        950
      • 30.6.6.1 Running a Performance Block Test

        950
      • 30.6.6.2 PM Block Monitoring

        950
      • 30.6.6.3 PM Block Generation

        951
        • Figure 30-18. FMC, BRC Insertion

          951
      • 30.6.6.4 BRC Performance Calculations

        952
  • 30.7 User-Defined Cells (UDC)

    952
    • Figure 30-19. Format of User-Defined Cells

      952
    • 30.7.1 UDC Extended Address Mode (UEAD)

      952
      • Figure 30-20. External CAM Address in UDC Extended Address Mode

        953
  • 30.8 ATM Layer Statistics

    953
  • 30.9 ATM-to-TDM Interworking

    953
    • 30.9.1 Automatic Data Forwarding

      953
      • Figure 30-21. ATM-to-TDM Interworking

        954
    • 30.9.2 Using Interrupts in Automatic Data Forwarding

      954
    • 30.9.3 Timing Issues

      955
    • 30.9.4 Clock Synchronization (SRTS and Adaptive FIFOs)

      955
    • 30.9.5 Mapping TDM Time Slots to VCs

      955
    • 30.9.6 CAS Support

      955
    • 30.9.7 Trunk Condition

      956
    • 30.9.8 ATM-to-ATM Data Forwarding

      956
  • 30.10 ATM Memory Structure

    956
    • 30.10.1 Parameter RAM

      956
      • Table 30-11. ATM Parameter RAM Map (continued)

        956
      • 30.10.1.1 Determining UEAD_OFFSET (UEAD Mode Only)

        959
        • Table 30-12. UEAD_OFFSETs for Extended Addresses in the UDC Extra Header

          959
      • 30.10.1.2 VCI Filtering (VCIF)

        959
        • Figure 30-22. VCI Filtering Enable Bits

          959
        • Table 30-13. VCI Filtering Enable Field Descriptions

          959
      • 30.10.1.3 Global Mode Entry (GMODE)

        960
        • Figure 30-23. Global Mode Entry (GMODE)

          960
        • Table 30-14. GMODE Field Descriptions (continued)

          960
    • 30.10.2 Connection Tables (RCT, TCT, and TCTE)

      961
      • Table 30-15. Receive and Transmit Connection Table Sizes

        961
      • 30.10.2.1 ATM Channel Code

        961
        • Figure 30-24. Example of a 1024-Entry Receive Connection Table

          962
      • 30.10.2.2 Receive Connection Table (RCT)

        962
        • Figure 30-25. Receive Connection Table (RCT) Entry

          963
        • Table 30-16. RCT Field Descriptions (continued)

          964
        • 30.10.2.2.1 AAL5 Protocol-Specific RCT

          965
          • Figure 30-26. AAL5 Protocol-Specific RCT

            966
          • Table 30-17. RCT Settings (AAL5 Protocol-Specific)

            966
        • 30.10.2.2.2 AAL5-ABR Protocol-Specific RCT

          966
          • Figure 30-27. AAL5-ABR Protocol-Specific RCT

            967
          • Table 30-18. ABR Protocol-Specific RCT Field Descriptions

            967
        • 30.10.2.2.3 AAL1 Protocol-Specific RCT

          967
          • Figure 30-28. AAL1 Protocol-Specific RCT

            967
          • Table 30-19. AAL1 Protocol-Specific RCT Field Descriptions (continued)

            968
        • 30.10.2.2.4 AAL0 Protocol-Specific RCT

          969
          • Figure 30-29. AAL0 Protocol-Specific RCT

            969
          • Table 30-20. AAL0-Specific RCT Field Descriptions (continued)

            969
        • 30.10.2.2.5 AAL1 CES Protocol-Specific RCT

          970
        • 30.10.2.2.6 AAL2 Protocol-Specific RCT

          970
      • 30.10.2.3 Transmit Connection Table (TCT)

        970
        • Figure 30-30. Transmit Connection Table (TCT) Entry

          970
        • Table 30-21. TCT Field Descriptions (continued)

          973
        • 30.10.2.3.1 AAL5 Protocol-Specific TCT

          975
          • Figure 30-31. AAL5 Protocol-Specific TCT

            975
          • Table 30-22. AAL5-Specific TCT Field Descriptions

            975
        • 30.10.2.3.2 AAL1 Protocol-Specific TCT

          975
          • Figure 30-32. AAL1 Protocol-Specific TCT

            976
          • Table 30-23. AAL1 Protocol-Specific TCT Field Descriptions

            976
        • 30.10.2.3.3 AAL0 Protocol-Specific TCT

          977
          • Figure 30-33. AAL0 Protocol-Specific TCT

            977
          • Table 30-24. AAL0-Specific TCT Field Descriptions

            977
        • 30.10.2.3.4 AAL1 CES Protocol-Specific TCT

          977
        • 30.10.2.3.5 AAL2 Protocol-Specific TCT

          977
        • 30.10.2.3.6 VBR Protocol-Specific TCTE

          977
          • Figure 30-34. Transmit Connection Table Extension (TCTE)-VBR Protocol-Specific

            978
          • Table 30-25. VBR-Specific TCTE Field Descriptions

            978
        • 30.10.2.3.7 UBR+ Protocol-Specific TCTE

          978
          • Figure 30-35. UBR+ Protocol-Specific TCTE

            979
          • Table 30-26. UBR+ Protocol-Specific TCTE Field Descriptions

            979
        • 30.10.2.3.8 ABR Protocol-Specific TCTE

          979
          • Figure 30-36. ABR Protocol-Specific TCTE

            980
          • Table 30-27. ABR-Specific TCTE Field Descriptions (continued)

            980
    • 30.10.3 OAM Performance Monitoring Tables

      982
      • Figure 30-37. OAM Performance Monitoring Table

        982
      • Table 30-28. OAM-Performance Monitoring Table Field Descriptions

        983
    • 30.10.4 APC Data Structure

      983
      • Figure 30-38. ATM Pace Control Data Structure

        984
      • 30.10.4.1 APC Parameter Tables

        984
        • Table 30-29. APC Parameter Table (continued)

          984
      • 30.10.4.2 APC Priority Table

        985
        • Table 30-30. APC Priority Table Entry

          985
      • 30.10.4.3 APC Scheduling Tables

        985
        • Figure 30-39. The APC Scheduling Table Structure

          985
        • Figure 30-40. Control Slot

          986
        • Table 30-31. Control Slot Field Description

          986
    • 30.10.5 ATM Controller Buffer Descriptors (BDs)

      986
      • 30.10.5.1 Transmit Buffer Operation

        986
        • Figure 30-41. Transmit Buffers and BD Table Example

          987
      • 30.10.5.2 Receive Buffer Operation

        987
        • 30.10.5.2.1 Static Buffer Allocation

          987
          • Figure 30-42. Receive Static Buffer Allocation Example

            988
        • 30.10.5.2.2 Global Buffer Allocation

          988
          • Figure 30-43. Receive Global Buffer Allocation Example

            989
        • 30.10.5.2.3 Free Buffer Pools

          989
          • Figure 30-44. Free Buffer Pool Structure

            989
          • Figure 30-45. Free Buffer Pool Entry

            990
          • Table 30-32. Free Buffer Pool Entry Field Descriptions

            990
        • 30.10.5.2.4 Free Buffer Pool Parameter Tables

          990
          • Table 30-33. Free Buffer Pool Parameter Table (continued)

            990
      • 30.10.5.3 ATM Controller Buffers

        991
        • Table 30-34. Receive and Transmit Buffers

          991
      • 30.10.5.4 AAL5 RxBD

        991
        • Figure 30-46. AAL5 RxBD

          991
        • Table 30-35. AAL5 RxBD Field Descriptions (continued)

          992
      • 30.10.5.5 AAL1 RxBD

        993
        • Figure 30-47. AAL1 RxBD

          993
        • Table 30-36. AAL1 RxBD Field Descriptions

          994
      • 30.10.5.6 AAL0 RxBD

        994
        • Figure 30-48. AAL0 RxBD

          994
        • Table 30-37. AAL0 RxBD Field Descriptions

          995
      • 30.10.5.7 AAL1 CES RxBD

        995
      • 30.10.5.8 AAL2 RxBD

        995
      • 30.10.5.9 AAL5, AAL1 CES User-Defined Cell-RxBD Extension

        996
        • Figure 30-49. User-Defined Cell-RxBD Extension

          996
      • 30.10.5.10 AAL5 TxBDs

        996
        • Figure 30-50. AAL5 TxBD

          996
        • Table 30-38. AAL5 TxBD Field Descriptions

          997
      • 30.10.5.11 AAL1 TxBDs

        997
        • Figure 30-51. AAL1 TxBD

          998
        • Table 30-39. AAL1 TxBD Field Descriptions

          998
      • 30.10.5.12 AAL0 TxBDs

        998
        • Figure 30-52. AAL0 TxBDs

          999
        • Table 30-40. AAL0 TxBD Field Descriptions

          999
      • 30.10.5.13 AAL1 CES TxBDs

        999
      • 30.10.5.14 AAL2 TxBDs

        1000
      • 30.10.5.15 AAL5, AAL1 User-Defined Cell-TxBD Extension

        1000
        • Figure 30-53. User-Defined Cell-TxBD Extension

          1000
    • 30.10.6 AAL1 Sequence Number (SN) Protection Table

      1000
      • Figure 30-54. AAL1 Sequence Number (SN) Protection Table

        1000
    • 30.10.7 UNI Statistics Table

      1001
      • Table 30-41. UNI Statistics Table

        1001
  • 30.11 ATM Exceptions

    1001
    • 30.11.1 Interrupt Queues

      1001
      • Figure 30-55. Interrupt Queue Structure

        1002
    • 30.11.2 Interrupt Queue Entry

      1002
      • Figure 30-56. Interrupt Queue Entry

        1002
      • Table 30-42. Interrupt Queue Entry Field Description

        1003
    • 30.11.3 Interrupt Queue Parameter Tables

      1003
      • Table 30-43. Interrupt Queue Parameter Table (continued)

        1003
  • 30.12 The UTOPIA Interface

    1004
    • 30.12.1 UTOPIA Interface Master Mode

      1004
      • Figure 30-57. UTOPIA Master Mode Signals

        1004
      • Table 30-44. UTOPIA Master Mode Signal Descriptions (continued)

        1004
      • 30.12.1.1 UTOPIA Master Multiple PHY Operation

        1005
    • 30.12.2 UTOPIA Interface Slave Mode

      1006
      • Figure 30-58. UTOPIA Slave Mode Signals

        1006
      • Table 30-45. UTOPIA Slave Mode Signals (continued)

        1006
      • 30.12.2.1 UTOPIA Slave Multiple PHY Operation

        1007
      • 30.12.2.2 UTOPIA Clocking Modes

        1007
      • 30.12.2.3 UTOPIA Loop-Back Modes

        1007
        • Table 30-46. UTOPIA Loop-Back Modes

          1007
  • 30.13 ATM Registers

    1007
    • 30.13.1 General FCC Mode Register (GFMR)

      1008
    • 30.13.2 FCC Protocol-Specific Mode Register (FPSMR)

      1008
      • Figure 30-59. FCC ATM Mode Register (FPSMR)

        1008
      • Table 30-47. FCC ATM Mode Register (FPSMR) (continued)

        1008
    • 30.13.3 ATM Event Register (FCCE)/Mask Register (FCCM)

      1010
      • Figure 30-60. ATM Event Register (FCCE)/FCC Mask Register (FCCM)

        1011
      • Table 30-48. FCCE/FCCM Field Descriptions

        1011
    • 30.13.4 FCC Transmit Internal Rate Registers (FTIRRx) (FCC1 and FCC2 Only)

      1011
      • Figure 30-61. FCC Transmit Internal Rate Registers (FTIRRx)

        1012
      • Table 30-49. FTIRRx Field Descriptions

        1012
      • Figure 30-62. FCC Transmit Internal Rate Clocking

        1012
  • 30.14 ATM Transmit Command

    1013
    • Figure 30-63. COMM_INFO Field

      1013
    • Table 30-50. COMM_INFO Field Descriptions

      1014
  • 30.15 SRTS Generation and Clock Recovery Using External Logic

    1014
    • Figure 30-64. AAL1 CES SRTS Generation Using External Logic

      1014
    • Figure 30-65. AAL1 CES SRTS Clock Recovery Using External Logic

      1015
  • 30.16 Configuring the ATM Controller for Maximum CPM Performance

    1015
    • 30.16.1 Using Transmit Internal Rate Mode

      1015
    • 30.16.2 APC Configuration

      1016
    • 30.16.3 Buffer Configuration

      1016
• Chapter 31 ATM AAL1 Circuit Emulation Service

  1017
  • 31.1 Features

    1017
  • 31.2 AAL1 CES Transmitter Overview

    1019
    • 31.2.1 Data Path

      1019
      • Figure 31-1. AAL1 Transmit Cell Format

        1019
      • Figure 31-2. AAL1 SDT Cells Type

        1019
    • 31.2.2 Signaling Path

      1019
      • Figure 31-3. AAL1 Framing Formats

        1020
  • 31.3 AAL1 CES Receiver Overview

    1020
    • Figure 31-4. AAL1 CES Receiver Data flow

      1022
  • 31.4 Interworking Functions

    1022
    • 31.4.1 Automatic Data Forwarding

      1022
      • 31.4.1.1 ATM-to-TDM

        1023
        • Figure 31-5. ATM-to-TDM Interworking

          1023
      • 31.4.1.2 TDM-to-ATM

        1023
        • Figure 31-6. TDM-to-ATM Interworking

          1024
    • 31.4.2 Timing Issues

      1024
    • 31.4.3 Clock Synchronization (SRTS, Adaptive FIFO)

      1025
    • 31.4.4 Mapping TDM Time Slots to VCs

      1025
    • 31.4.5 Trunk Condition

      1026
    • 31.4.6 Channel Associated Signaling (CAS) Support

      1026
      • Figure 31-7. Mapping CAS Data on a Serial Interface

        1026
      • Figure 31-8. Internal CAS Block Formats

        1027
    • 31.4.7 Mapping VC Signaling to CAS Blocks

      1027
      • Figure 31-9. Mapping CAS Entry

        1028
      • 31.4.7.1 CAS Routing Table

        1028
        • Figure 31-10. AAL1 CES CAS Routing Table (CRT)

          1028
        • Figure 31-11. AAL1 CES CAS Routing Table Entry

          1028
        • Table 31-1. CAS Routing Table Entry Field Descriptions

          1029
      • 31.4.7.2 TDM-to-ATM CAS Support

        1029
        • Figure 31-12. CAS Flow TDM-to-ATM

          1029
        • 31.4.7.2.1 CAS Mapping Using the Core (Optional)

          1030
      • 31.4.7.3 ATM-to-TDM CAS Support

        1030
        • Figure 31-13. CAS Flow ATM-to-TDM

          1030
        • 31.4.7.3.1 CAS Updates Using the Core (Optional)

          1031
  • 31.5 ATM-to-TDM Adaptive Slip Control

    1031
    • Figure 31-14. Data Structure for ATM-to-TDM Adaptive Slip Control

      1032
    • 31.5.1 CES Adaptive Threshold Tables

      1032
      • Figure 31-15. CES Adaptive Threshold Table

        1033
      • Table 31-2. CES Adaptive Threshold Table Field Descriptions

        1033
      • Figure 31-16. Pre-Underrun Sequence

        1034
      • Figure 31-17. Pre-Overrun Sequence

        1035
  • 31.6 3-Step-SN Algorithm

    1036
    • 31.6.1 The Three States of the Algorithm

      1036
      • Figure 31-18. Recoverable Sync Fail sequence options

        1036
      • Figure 31-19. 3-Step-SN-Algorithm

        1037
  • 31.7 Pointer Verification Mechanism

    1037
    • Figure 31-20. Pointer verification mechanism

      1038
  • 31.8 AAL-1 Memory Structure

    1038
    • 31.8.1 AAL1 CES Parameter RAM

      1038
      • Table 31-3. AAL1 CES Field Descriptions (continued)

        1038
      • Table 31-4. AAL1 CES Parameters

        1041
  • 31.9 Receive and Transmit Connection Tables (RCT, TCT)

    1041
    • 31.9.1 Receive Connection Table (RCT)

      1042
      • Figure 31-21. Receive Connection Table (RCT) Entry

        1042
      • Table 31-5. RCT Field Descriptions (continued)

        1043
      • 31.9.1.1 AAL1 CES Protocol-Specific RCT

        1044
        • Figure 31-22. AAL1 CES Protocol-Specific RCT

          1044
        • Table 31-6. AAL1 CES Protocol-Specific RCT Field Descriptions (continued)

          1045
    • 31.9.2 Transmit Connection Table (TCT)

      1047
      • Figure 31-23. Transmit Connection Table (TCT) Entry

        1047
      • Table 31-7. TCT Field Descriptions (continued)

        1048
      • 31.9.2.1 AAL1 CES Protocol-Specific TCT

        1050
        • Figure 31-24. AAL1 CES Protocol-Specific TCT

          1050
        • Table 31-8. AAL1 CES Protocol-Specific TCT Field Descriptions (continued)

          1050
  • 31.10 Outgoing CAS Status Register (OCASSR)

    1051
    • Figure 31-25. Outgoing CAS Status Register (OCASSR)

      1051
    • Table 31-9. OCASSR Field Descriptions

      1051
  • 31.11 Buffer Descriptors

    1052
    • 31.11.1 Transmit Buffer Operation

      1052
      • Figure 31-26. Transmit Buffers and BD Table Example

        1053
    • 31.11.2 Receive Buffer Operation

      1053
      • Figure 31-27. Receive Buffers and BD Table Example

        1054
  • 31.12 ATM Controller Buffers

    1054
    • Table 31-10. Receive and Transmit Buffers

      1054
    • 31.12.1 AAL1 CES RxBD

      1054
      • Figure 31-28. AAL1 CES RxBD

        1055
      • Table 31-11. AAL1 CES RxBD Field Descriptions

        1055
    • 31.12.2 AAL1 CES TxBDs

      1056
      • Figure 31-29. AAL1 CES TxBD

        1056
      • Table 31-12. AAL1 CES TxBD Field Descriptions (continued)

        1056
  • 31.13 AAL1 CES Exceptions

    1057
    • 31.13.1 AAL1 CES Interrupt Queue Entry

      1057
      • Figure 31-30. AAL1 CES Interrupt Queue Entry

        1057
      • Table 31-13. AAL1 CES Interrupt Queue Entry Field Descriptions (continued)

        1057
  • 31.14 AAL1 Sequence Number (SN) Protection Table

    1058
    • Figure 31-31. AAL1 Sequence Number (SN) Protection Table

      1059
  • 31.15 Internal AAL1 CES Statistics Tables

    1059
    • Table 31-14. AAL1 CES DPR Statistics Table

      1059
  • 31.16 External AAL1 CES Statistics Tables

    1060
    • Table 31-15. AAL1 CES External Statistics Table

      1060
  • 31.17 CES-Specific Additions to the MCC

    1060
  • 31.18 Application Considerations

    1060
    • Figure 31-32. TDM-to-ATM Timing Issue

      1061
• Chapter 32 ATM AAL2

  1063
  • 32.1 Introduction

    1063
    • Figure 32-1. AAL2 Data Units

      1063
    • Figure 32-2. AAL2 Sublayer Structure

      1064
    • Figure 32-3. AAL2 Switching Example

      1065
  • 32.2 Features

    1065
  • 32.3 AAL2 Transmitter

    1067
    • 32.3.1 Transmitter Overview

      1067
    • 32.3.2 Transmit Priority Mechanism

      1067
      • 32.3.2.1 Round Robin Priority

        1068
        • Figure 32-4. Round Robin Priority

          1068
      • 32.3.2.2 Fixed Priority

        1068
        • Figure 32-5. Fixed Priority Mode

          1069
    • 32.3.3 Partial Fill Mode (PFM)

      1069
    • 32.3.4 No STF Mode

      1070
    • 32.3.5 AAL2 Tx Data Structures

      1070
      • 32.3.5.1 AAL2 Protocol-Specific TCT

        1071
        • Figure 32-6. AAL2 Protocol-Specific Transmit Connection Table (TCT)

          1071
        • Table 32-1. AAL2 Protocol-Specific Transmit Connection Table (TCT) Field Descriptions (continued)

          1073
      • 32.3.5.2 CPS Tx Queue Descriptor

        1075
        • Figure 32-7. CPS Tx Queue Descriptor (TxQD)

          1076
        • Table 32-2. CPS TxQD Field Descriptions (continued)

          1076
      • 32.3.5.3 CPS Buffer Structure

        1077
        • Figure 32-8. Buffer Structure Example for CPS Packets

          1077
        • Figure 32-9. CPS TxBD

          1078
        • Table 32-3. CPS TxBD Field Descriptions

          1078
        • Figure 32-10. CPS Packet Header Format

          1079
      • 32.3.5.4 SSSAR Tx Queue Descriptor

        1079
        • Figure 32-11. SSSAR Tx Queue Descriptor

          1079
        • Table 32-4. SSSAR TxQD Field Descriptions

          1080
      • 32.3.5.5 SSSAR Transmit Buffer Descriptor

        1081
        • Figure 32-12. SSSAR TxBD

          1081
        • Table 32-5. SSSAR TxBD Field Descriptions (continued)

          1081
  • 32.4 AAL2 Receiver

    1082
    • 32.4.1 Receiver Overview

      1082
    • 32.4.2 Mapping of PHY | VP | VC | CID

      1083
      • Figure 32-13. CID Mapping Process

        1084
    • 32.4.3 AAL2 Switching

      1084
      • Figure 32-14. AAL2 Switching

        1085
    • 32.4.4 AAL2 RX Data Structures

      1085
      • 32.4.4.1 AAL2 Protocol-Specific RCT

        1086
        • Figure 32-15. AAL2 Protocol-Specific Receive Connection Table (RCT)

          1086
        • Table 32-6. AAL2 Protocol-Specific RCT Field Descriptions

          1087
      • 32.4.4.2 CID Mapping Tables and RxQDs

        1089
      • 32.4.4.3 CPS Rx Queue Descriptors

        1089
        • Figure 32-16. CPS Rx Queue Descriptor

          1089
        • Table 32-7. CPS RxQD Field Descriptions

          1090
      • 32.4.4.4 CPS Receive Buffer Descriptor (RxBD)

        1090
        • Figure 32-17. CPS Receive Buffer Descriptor

          1090
        • Table 32-8. CPS RxBD Field Descriptions

          1091
      • 32.4.4.5 CPS Switch Rx Queue Descriptor

        1091
        • Figure 32-18. CPS Switch Rx Queue Descriptor

          1092
        • Table 32-9. CPS Switch RxQD Field Descriptions

          1092
      • 32.4.4.6 SWITCH Receive/Transmit Buffer Descriptor (RxBD)

        1092
        • Figure 32-19. Switch Receive/Transmit Buffer Descriptor

          1092
        • Table 32-10. Switch RxBD Field Descriptions

          1093
      • 32.4.4.7 SSSAR Rx Queue Descriptor

        1093
        • Figure 32-20. SSSAR Rx Queue Descriptor

          1094
        • Table 32-11. SSSAR RxQD Field Descriptions (continued)

          1094
      • 32.4.4.8 SSSAR Receive Buffer Descriptor

        1095
        • Figure 32-21. SSSAR Receive Buffer Descriptor

          1095
        • Table 32-12. SSSAR RxBD Field Descriptions

          1096
  • 32.5 AAL2 Parameter RAM

    1097
    • Table 32-13. AAL2 Parameter RAM (continued)

      1097
  • 32.6 User-Defined Cells in AAL2

    1100
    • Figure 32-22. UDC Header Table

      1100
  • 32.7 AAL2 Exceptions

    1100
    • Figure 32-23. AAL2 Interrupt Queue Entry CID ¹ 0

      1101
    • Table 32-14. AAL2 Interrupt Queue Entry CID ¹ 0 Field Descriptions

      1101
    • Figure 32-24. AAL2 Interrupt Queue Entry CID = 0

      1101
    • Table 32-15. AAL2 Interrupt Queue Entry CID = 0 Field Descriptions

      1102
• Chapter 33 Inverse Multiplexing for ATM (IMA)

  1103
  • 33.1 Features

    1103
    • Table 33-1. IMA Sublayer in Layer Reference Model

      1104
    • 33.1.1 References

      1105
    • 33.1.2 IMA Versions Supported

      1105
    • 33.1.3 PowerQUICC II Versions Supported

      1105
    • 33.1.4 PHY-Layer Devices Supported

      1105
    • 33.1.5 ATM Features Not Supported

      1106
    • 33.1.6 Additional Impact on PowerQUICC II Features

      1106
  • 33.2 IMA Protocol Overview

    1106
    • 33.2.1 Introduction

      1106
      • Figure 33-1. Basic Concept of IMA

        1107
    • 33.2.2 IMA Frame Overview

      1107
      • Figure 33-2. Illustration of IMA Frames

        1108
      • Figure 33-3. IMA Microcode Overview

        1108
    • 33.2.3 Overview of IMA Cells

      1109
      • 33.2.3.1 IMA Control Cells

        1109
        • Figure 33-4. IMA Frame and ICP Cell Formats

          1112
      • 33.2.3.2 IMA Filler Cells

        1112
  • 33.3 IMA Microcode Architecture

    1112
    • 33.3.1 IMA Function Partitioning

      1112
      • 33.3.1.1 User Plane Functions Performed by Microcode

        1113
      • 33.3.1.2 Plane Management Functions Performed by Microcode

        1113
    • 33.3.2 Transmit Architecture

      1113
      • Figure 33-5. IMA Transmit Task Interaction

        1114
      • 33.3.2.1 TRL Operation

        1114
        • 33.3.2.1.1 TRL Service Latency

          1115
      • 33.3.2.2 Non-TRL Operation

        1115
      • 33.3.2.3 Transmit Queue Operation Examples (ITC mode)

        1116
        • Figure 33-6. Transmit Queue Normal Operating State

          1116
        • Figure 33-7. Transmit Queue Behavior: Link Clock Rate Same as TRL

          1116
        • Figure 33-8. Transmit Queue Behavior: Link Clock Rate Slower than TRL

          1117
        • Figure 33-9. Transmit Queue Behavior: Link Clock Rate Faster than TRL, Worst-Case Event Sequence

          1118
      • 33.3.2.4 Differences in CTC Operation

        1118
    • 33.3.3 Receive Architecture

      1119
      • Figure 33-10. IMA Receive Task Interaction

        1119
      • 33.3.3.1 Cell Reception Task

        1119
        • Figure 33-11. IMA Microcode: Receive Process

          1123
      • 33.3.3.2 Cell Processing Activation Function

        1124
        • 33.3.3.2.1 On-Demand Cell Processing

          1124
        • 33.3.3.2.2 IDCR-Regulated Cell Processing

          1125
      • 33.3.3.3 Cell Processing Task

        1126
  • 33.4 IMA Programming Model

    1126
    • 33.4.1 Data Structure Organization

      1126
      • Figure 33-12. IMA Root Table Data Structures

        1127
    • 33.4.2 IMA FCC Programming

      1128
      • 33.4.2.1 FCC Registers

        1128
        • 33.4.2.1.1 FPSMRx

          1128
        • 33.4.2.1.2 FTIRRx

          1128
      • 33.4.2.2 FCC Parameters

        1128
        • 33.4.2.2.1 TCELL_TMP_BASE and RCELL_TMP_BASE

          1128
        • 33.4.2.2.2 GMODE

          1128
      • 33.4.2.3 IMA-Specific FCC Parameters

        1128
        • Table 33-2. FCC Parameter RAM Additions

          1128
    • 33.4.3 IMA Root Table

      1129
      • Table 33-3. IMA Root Table (continued)

        1129
      • 33.4.3.1 IMA Control (IMACNTL)

        1131
        • Figure 33-13. IMA Control (IMACNTL)

          1131
        • Table 33-4. IMACNTL Field Descriptions

          1131
    • 33.4.4 IMA Group Tables

      1131
      • 33.4.4.1 IMA Group Transmit Table Entry

        1132
        • Table 33-5. IMA Group Transmit Table Entry (continued)

          1132
        • 33.4.4.1.1 IMA Group Transmit Control (IGTCNTL)

          1133
          • Figure 33-14. IMA Group Transmit Control (IGTCNTL)

            1133
          • Table 33-6. IGTCNTL Field Descriptions

            1133
        • 33.4.4.1.2 IMA Group Transmit State (IGTSTATE)

          1133
          • Figure 33-15. IMA Group Transmit State (IGTSTATE)

            1134
          • Table 33-7. IGTSTATE Field Descriptions

            1134
        • 33.4.4.1.3 Transmit Group Order Table

          1134
          • Figure 33-16. Transmit Group Order Table Entry

            1134
          • Table 33-8. Transmit Group Order Table Entry Field Descriptions

            1135
        • 33.4.4.1.4 ICP Cell Templates

          1135
          • Table 33-9. ICP Cell Template (continued)

            1135
      • 33.4.4.2 IMA Group Receive Table Entry

        1138
        • Table 33-10. IMA Group Receive Table Entry (continued)

          1138
        • 33.4.4.2.1 IMA Group Receive Control (IGRCNTL)

          1140
          • Figure 33-17. IMA Group Receive Control (IGRCNTL)

            1140
          • Table 33-11. IGRCNTL Field Descriptions

            1141
        • 33.4.4.2.2 IMA Group Receive State (IGRSTATE)

          1141
          • Figure 33-18. IMA Group Receive State (IGRSTATE)

            1141
          • Table 33-12. IGRSTATE Field Descriptions

            1141
        • 33.4.4.2.3 IMA Receive Group Frame Size

          1141
          • Figure 33-19. IMA Receive Group Frame Size (IGRSTATE)

            1142
          • Table 33-13. IRGFS Field Descriptions

            1142
        • 33.4.4.2.4 Receive Group Order Tables

          1142
          • Figure 33-20. Receive Group Order Table Entry

            1142
          • Table 33-14. Receive Group Order Table Entry Field Descriptions

            1143
    • 33.4.5 IMA Link Tables

      1143
      • 33.4.5.1 IMA Link Transmit Table Entry

        1143
        • Table 33-15. IMA Link Transmit Table Entry (continued)

          1143
        • 33.4.5.1.1 IMA Link Transmit Control (ILTCNTL)

          1144
          • Figure 33-21. IMA Link Transmit Control (ILTCNTL)

            1144
          • Table 33-16. ILTCNTL Field Descriptions (continued)

            1144
        • 33.4.5.1.2 IMA Link Transmit State (ILTSTATE)

          1145
          • Figure 33-22. IMA Link Transmit State (ILTSTATE)

            1145
          • Table 33-17. ILTSTATE Field Descriptions

            1145
        • 33.4.5.1.3 IMA Transmit Interrupt Status (ITINTSTAT)

          1145
          • Figure 33-23. IMA Transmit Interrupt Status (ITINTSTAT)

            1145
          • Table 33-18. ITINTSTAT Field Descriptions

            1146
      • 33.4.5.2 IMA Link Receive Table Entry

        1146
        • Table 33-19. IMA Link Receive Table Entry (continued)

          1146
        • 33.4.5.2.1 IMA Link Receive Control (ILRCNTL)

          1148
          • Figure 33-24. IMA Link Receive Control (ILRCNTL)

            1148
          • Table 33-20. ILRCNTL Field Descriptions

            1148
        • 33.4.5.2.2 IMA Link Receive State (ILRSTATE)

          1149
          • Figure 33-25. IMA Link Receive State (ILRSTATE)

            1149
          • Table 33-21. ILRSTATE Field Descriptions

            1149
      • 33.4.5.3 IMA Link Receive Statistics Table

        1150
        • Table 33-22. IMA Link Receive Statistics Table Entry

          1150
    • 33.4.6 Structures in External Memory

      1150
      • 33.4.6.1 Transmit Queues

        1150
        • Figure 33-26. IMA Transmit Queue

          1150
      • 33.4.6.2 Delay Compensation Buffers (DCB)

        1151
        • Figure 33-27. Cell Buffer in Delay Compensation Buffer

          1151
        • Figure 33-28. IMA Delay Compensation Buffer

          1151
    • 33.4.7 IMA Exceptions

      1151
      • 33.4.7.1 IMA Interrupt Queue Entry

        1152
        • Figure 33-29. IMA Interrupt Queue Entry

          1152
        • Table 33-23. IMA Interrupt Queue Entry Field Descriptions

          1153
      • 33.4.7.2 ICP Cell Reception Exceptions

        1153
    • 33.4.8 IDCR Timer Programming

      1154
      • 33.4.8.1 IDCR Master Clock

        1154
      • 33.4.8.2 IDCR FCC Parameter Shadow

        1154
        • 33.4.8.2.1 PowerQUICC II Features Unavailable if IDCR is Used

          1154
          • Table 33-24. Unavailable Features when DREQx used as IDCR Master Clock

            1155
        • 33.4.8.2.2 Programming the FCC Parameter Shadow

          1155
        • 33.4.8.2.3 On-the-Fly Changes of FCC Parameters

          1155
      • 33.4.8.3 IDCR_Init Command

        1156
      • 33.4.8.4 IDCR Root Parameters

        1156
        • Table 33-25. IDCR IMA Root Parameters

          1156
      • 33.4.8.5 IDCR Table Entry

        1156
        • Table 33-26. IDCR Table Entry

          1156
      • 33.4.8.6 IDCR Counter Algorithm

        1157
      • 33.4.8.7 IDCR Events

        1157
        • Figure 33-30. IDMA Event/Mask Registers in IDCR Mode (IDSR/IDMR)

          1157
        • Table 33-27. IDSR/IDMR Field Descriptions (continued)

          1157
    • 33.4.9 APC Programming for IMA

      1158
      • Table 33-28. Examples of APC Programming for IMA

        1158
      • 33.4.9.1 Programming for CBR, UBR, VBR, and UBR+

        1159
      • 33.4.9.2 Programming for ABR

        1159
    • 33.4.10 Changing IMA Version

      1160
      • Figure 33-31. COMM_INFO Field

        1160
      • Table 33-29. COMM_INFO Field Descriptions

        1160
  • 33.5 IMA Software Interface and Requirements

    1160
    • 33.5.1 Software Model

      1160
      • Figure 33-32. IMA Microcode/Software Interaction

        1161
    • 33.5.2 Initialization Procedure

      1161
    • 33.5.3 Software Responsibilities

      1161
      • 33.5.3.1 System Definition

        1161
      • 33.5.3.2 General Operation

        1162
      • 33.5.3.3 Receive Link State Machine Control

        1162
      • 33.5.3.4 Receive Group State Machine Control

        1162
      • 33.5.3.5 Transmit Link State Machine Control

        1162
      • 33.5.3.6 Transmit Group State Machine Control

        1163
      • 33.5.3.7 Group Symmetry Control

        1163
      • 33.5.3.8 ICP End-to-End Channel Transmission

        1163
      • 33.5.3.9 Link Addition and Slow Recovery (LASR) Procedure

        1163
      • 33.5.3.10 Failure Alarms

        1163
      • 33.5.3.11 Test Pattern Control

        1164
      • 33.5.3.12 Performance Parameter Measurement and Reporting

        1164
      • 33.5.3.13 SNMP MIBs

        1164
    • 33.5.4 IMA Software Procedures

      1164
      • 33.5.4.1 Transmit ICP Cell Signalling

        1164
      • 33.5.4.2 Receive Link Start-up Procedure

        1164
      • 33.5.4.3 Group Start-up Procedure

        1165
        • 33.5.4.3.1 As Initiator (TX)

          1166
          • Figure 33-33. Near-End versus Far-End

            1167
        • 33.5.4.3.2 As Responder (RX)

          1167
      • 33.5.4.4 Link Addition Procedure

        1167
        • 33.5.4.4.1 Rx Steps

          1167
        • 33.5.4.4.2 TX Parameters

          1168
      • 33.5.4.5 Link Removal Procedure

        1169
        • 33.5.4.5.1 Rx Steps

          1169
        • 33.5.4.5.2 TX Parameters

          1170
      • 33.5.4.6 Link Receive Deactivation Procedure

        1170
      • 33.5.4.7 Link Receive Reactivation Procedure

        1171
      • 33.5.4.8 TRL On-the-Fly Change Procedure

        1171
      • 33.5.4.9 Transmit Event Response Procedures

        1172
      • 33.5.4.10 Receive Event Response Procedures

        1172
      • 33.5.4.11 Test Pattern Procedure

        1174
        • 33.5.4.11.1 As Initiator (NE)

          1174
        • 33.5.4.11.2 As Responder (FE)

          1174
      • 33.5.4.12 IDCR Operation

        1175
        • 33.5.4.12.1 IDCR Start-up

          1175
        • 33.5.4.12.2 Activating a Group in IDCR Mode

          1176
      • 33.5.4.13 End-to-End Channel Signalling Procedure

        1176
        • 33.5.4.13.1 Transmit

          1176
        • 33.5.4.13.2 Receive

          1177
• Chapter 34 ATM Transmission Convergence Layer

  1179
  • Figure 34-1. Serial ATM Using FCC2 and TC Blocks (Single Channel)

    1179
  • 34.1 Features

    1179
  • 34.2 Functionality

    1181
    • Figure 34-2. TC Layer Block Diagram

      1182
    • 34.2.1 Receive ATM Cell Functions

      1182
      • Figure 34-3. TC Cell Delineation State Machine

        1183
      • Figure 34-4. HEC: Receiver Modes of Operation

        1184
      • 34.2.1.1 Receive ATM 2-Cell FIFO

        1184
    • 34.2.2 Transmit ATM Cell Functions

      1184
      • 34.2.2.1 Transmit ATM 2-Cell FIFO

        1184
    • 34.2.3 Receive UTOPIA Interface

      1185
    • 34.2.4 Transmit UTOPIA Interface

      1185
  • 34.3 Signals

    1185
    • Table 34-1. TC Layer Signals

      1185
  • 34.4 TC Layer Programming Mode

    1185
    • 34.4.1 TC Layer Registers

      1185
      • 34.4.1.1 TC Layer Mode Register [1-8] (TCMODEx)

        1185
        • Figure 34-5. TC Layer Mode Register (TCMODEx)

          1186
        • Table 34-2. TCMODEx Field Descriptions (continued)

          1186
      • 34.4.1.2 Cell Delineation State Machine Register [1-8] (CDSMRx)

        1187
        • Figure 34-6. Cell Delineation State Machine Register (CDSMRx)

          1187
        • Table 34-3. CDSMRx Field Descriptions

          1187
      • 34.4.1.3 TC Layer Event Register [1-8] (TCERx)

        1188
        • Figure 34-7. TC Layer Event Register (TCERx)

          1188
        • Table 34-4. TCERx Field Descriptions

          1188
      • 34.4.1.4 TC Layer Mask Register (TCMRx)

        1189
    • 34.4.2 TC Layer General Registers

      1189
      • 34.4.2.1 TC Layer General Event Register (TCGER)

        1189
        • Figure 34-8. TC Layer General Event Register (TCGER)

          1189
        • Table 34-5. TCGER Field Descriptions

          1189
      • 34.4.2.2 TC Layer General Status Register (TCGSR)

        1189
        • Figure 34-9. TC Layer General Status Register (TCGSR)

          1190
        • Table 34-6. TCGSR Field Descriptions

          1190
    • 34.4.3 TC Layer Cell Counters

      1190
      • 34.4.3.1 Received Cell Counter [1-8] (TC_RCCx)

        1190
      • 34.4.3.2 Transmitted Cell Counter [1-8] (TC_TCCx)

        1190
      • 34.4.3.3 Errored Cell Counter [1-8] (TC_ECCx)

        1190
      • 34.4.3.4 Corrected Cell Counter [1-8] (TC_CCCx)

        1190
      • 34.4.3.5 Transmitted IDLE Cell Counter [1-8] (TC_ICCx)

        1190
      • 34.4.3.6 Filtered Cell Counter [1-8] (TC_FCCx)

        1191
    • 34.4.4 Programming FCC2

      1191
    • 34.4.5 Programming and Operating the TC Layer

      1191
      • 34.4.5.1 Receive

        1191
      • 34.4.5.2 Transmit

        1191
        • Figure 34-10. TC Operation in FCC External Rate Mode

          1192
        • Figure 34-11. TC Operation in FCC Internal Rate Mode (Sub Rate Mode)

          1193
  • 34.5 Implementation Example

    1193
    • Figure 34-12. Example of Serial ATM Application

      1194
    • 34.5.1 Operating the TC Layer at Higher Frequencies

      1194
    • 34.5.2 Programming a T1 Application

      1194
    • Step 1

      1195
      • Table 34-7. Programming GFMR and FPSMR to Setup the FCC2

        1195
    • Step 2

      1195
    • Step 3

      1195
      • Table 34-8. Enable FCC2

        1195
    • Step 4

      1195
      • Table 34-9. Programming the CPM MUX for a TI Application

        1195
    • Step 5

      1195
      • Table 34-10. Programming the TC Layer Block

        1195
    • Step 6

      1196
      • Table 34-11. Programming the SI RAM (Rx or Tx) for a T1 Application

        1196
    • Step 7

      1196
      • Table 34-12. Programming SI Registers to Enable TDM

        1196
• Chapter 35 Fast Ethernet Controller

  1197
  • Figure 35-1. Ethernet Frame Structure

    1197
  • 35.1 Fast Ethernet on the PowerQUICC II

    1198
    • Figure 35-2. Ethernet Block Diagram

      1198
  • 35.2 Features

    1198
  • 35.3 Connecting the PowerQUICC II to Fast Ethernet

    1200
    • Figure 35-3. Connecting the PowerQUICC II to Ethernet

      1200
  • 35.4 Ethernet Channel Frame Transmission

    1201
  • 35.5 Ethernet Channel Frame Reception

    1202
  • 35.6 Flow Control

    1203
    • Table 35-1. Flow Control Frame Structure

      1203
  • 35.7 CAM Interface

    1203
  • 35.8 Ethernet Parameter RAM

    1204
    • Table 35-2. Ethernet-Specific Parameter RAM (continued)

      1204
  • 35.9 Programming Model

    1207
  • 35.10 Ethernet Command Set

    1207
    • Table 35-3. Transmit Commands

      1208
    • Table 35-4. Receive Commands

      1208
  • 35.11 RMON Support

    1209
    • Table 35-5. RMON Statistics and Counters (continued)

      1209
  • 35.12 Ethernet Address Recognition

    1210
    • Figure 35-4. Ethernet Address Recognition Flowchart

      1212
  • 35.13 Hash Table Algorithm

    1212
  • 35.14 Interpacket Gap Time

    1213
  • 35.15 Handling Collisions

    1213
  • 35.16 Internal and External Loopback

    1213
  • 35.17 Ethernet Error-Handling Procedure

    1213
    • Table 35-6. Transmission Errors

      1214
    • Table 35-7. Reception Errors

      1214
  • 35.18 Fast Ethernet Registers

    1214
    • 35.18.1 FCC Ethernet Mode Register (FPSMR)

      1214
      • Figure 35-5. FCC Ethernet Mode Registers (FPSMR)

        1215
      • Table 35-8. FPSMR Ethernet Field Descriptions (continued)

        1215
    • 35.18.2 Ethernet Event Register (FCCE)/Mask Register (FCCM)

      1216
      • Figure 35-6. Ethernet Event Register (FCCE)/Mask Register (FCCM)

        1216
      • Table 35-9. FCCE/FCCM Field Descriptions

        1217
      • Figure 35-7. Ethernet Interrupt Events Example

        1218
  • 35.19 Ethernet RxBDs

    1218
    • Figure 35-8. Fast Ethernet Receive Buffer (RxBD)

      1219
    • Table 35-10. RxBD Field Descriptions (continued)

      1219
    • Figure 35-9. Ethernet Receiving Using RxBDs

      1221
  • 35.20 Ethernet TxBDs

    1221
    • Figure 35-10. Fast Ethernet Transmit Buffer (TxBD)

      1222
    • Table 35-11. Ethernet TxBD Field Definitions (continued)

      1222
• Chapter 36 FCC HDLC Controller

  1225
  • 36.1 Key Features

    1225
  • 36.2 HDLC Channel Frame Transmission Processing

    1226
    • Figure 36-1. HDLC Framing Structure

      1226
  • 36.3 HDLC Channel Frame Reception Processing

    1227
  • 36.4 HDLC Parameter RAM

    1227
    • Table 36-1. FCC HDLC-Specific Parameter RAM Memory Map (continued)

      1227
    • Figure 36-2. HDLC Address Recognition Example

      1229
  • 36.5 Programming Model

    1229
    • 36.5.1 HDLC Command Set

      1229
      • Table 36-2. Transmit Commands (continued)

        1229
      • Table 36-3. Receive Commands

        1230
    • 36.5.2 HDLC Error Handling

      1230
      • Table 36-4. HDLC Transmission Errors

        1230
      • Table 36-5. HDLC Reception Errors

        1231
  • 36.6 HDLC Mode Register (FPSMR)

    1231
    • Figure 36-3. HDLC Mode Register (FPSMR)

      1232
    • Table 36-6. FPSMR Field Descriptions (continued)

      1232
  • 36.7 HDLC Receive Buffer Descriptor (RxBD)

    1233
    • Figure 36-4. FCC HDLC Receiving Using RxBDs

      1234
    • Figure 36-5. FCC HDLC Receive Buffer Descriptor (RxBD)

      1235
    • Table 36-7. RxBD field Descriptions (continued)

      1235
  • 36.8 HDLC Transmit Buffer Descriptor (TxBD)

    1236
    • Figure 36-6. FCC HDLC Transmit Buffer Descriptor (TxBD)

      1236
    • Table 36-8. HDLC TxBD Field Descriptions

      1237
  • 36.9 HDLC Event Register (FCCE)/Mask Register (FCCM)

    1238
    • Figure 36-7. HDLC Event Register (FCCE)/Mask Register (FCCM)

      1238
    • Table 36-9. FCCE/FCCM Field Descriptions

      1239
    • Figure 36-8. HDLC Interrupt Event Example

      1240
  • 36.10 FCC Status Register (FCCS)

    1240
    • Figure 36-9. FCC Status Register (FCCS)

      1240
    • Table 36-10. FCCS Register Field Descriptions

      1241
• Chapter 37 FCC Transparent Controller

  1243
  • 37.1 Features

    1243
  • 37.2 Transparent Channel Operation

    1244
  • 37.3 Achieving Synchronization in Transparent Mode

    1244
    • 37.3.1 In-Line Synchronization Pattern

      1244
      • Figure 37-1. In-Line Synchronization Pattern

        1244
    • 37.3.2 External Synchronization Signals

      1245
    • 37.3.3 Transparent Synchronization Example

      1245
      • Figure 37-2. Sending Transparent Frames between PowerQUICC IIs

        1246
• Chapter 38 Serial Peripheral Interface (SPI)

  1247
  • Figure 38-1. SPI Block Diagram

    1247
  • 38.1 Features

    1247
  • 38.2 SPI Clocking and Signal Functions

    1248
  • 38.3 Configuring the SPI Controller

    1249
    • 38.3.1 The SPI as a Master Device

      1249
      • Figure 38-2. Single-Master/Multi-Slave Configuration

        1249
    • 38.3.2 The SPI as a Slave Device

      1250
    • 38.3.3 The SPI in Multimaster Operation

      1250
      • Figure 38-3. Multimaster Configuration

        1251
  • 38.4 Programming the SPI Registers

    1252
    • 38.4.1 SPI Mode Register (SPMODE)

      1252
      • Figure 38-4. SPMODE-SPI Mode Register

        1252
      • Table 38-1. SPMODE Field Descriptions (continued)

        1252
      • Figure 38-5. SPI Transfer Format with SPMODE[CP] = 0

        1253
      • Figure 38-6. SPI Transfer Format with SPMODE[CP] = 1

        1254
      • 38.4.1.1 SPI Examples with Different SPMODE[LEN] Values

        1254
        • Table 38-2. Example Conventions

          1254
    • 38.4.2 SPI Event/Mask Registers (SPIE/SPIM)

      1255
      • Figure 38-7. SPIE/SPIM-SPI Event/Mask Registers

        1255
      • Table 38-3. SPIE/SPIM Field Descriptions

        1255
    • 38.4.3 SPI Command Register (SPCOM)

      1256
      • Figure 38-8. SPCOM-SPI Command Register

        1256
      • Table 38-4. SPCOM Field Descriptions

        1256
  • 38.5 SPI Parameter RAM

    1256
    • Table 38-5. SPI Parameter RAM Memory Map

      1257
    • 38.5.1 Receive/Transmit Function Code Registers (RFCR/TFCR)

      1258
      • Figure 38-9. RFCR/TFCR-Function Code Registers

        1258
      • Table 38-6. RFCR/TFCR Field Descriptions

        1258
  • 38.6 SPI Commands

    1258
    • Table 38-7. SPI Commands (continued)

      1258
  • 38.7 The SPI Buffer Descriptor (BD) Table

    1259
    • Figure 38-10. SPI Memory Structure

      1259
    • 38.7.1 SPI Buffer Descriptors (BDs)

      1259
      • 38.7.1.1 SPI Receive BD (RxBD)

        1260
        • Figure 38-11. SPI RxBD

          1260
        • Table 38-8. SPI RxBD Status and Control Field Descriptions (continued)

          1260
      • 38.7.1.2 SPI Transmit BD (TxBD)

        1261
        • Figure 38-12. SPI TxBD

          1261
        • Table 38-9. SPI TxBD Status and Control Field Descriptions (continued)

          1261
  • 38.8 SPI Master Programming Example

    1262
  • 38.9 SPI Slave Programming Example

    1263
  • 38.10 Handling Interrupts in the SPI

    1264
• Chapter 39 I2C Controller

  1265
  • Figure 39-1. I2C Controller Block Diagram

    1265
  • 39.1 Features

    1266
  • 39.2 I2C Controller Clocking and Signal Functions

    1266
    • Figure 39-2. I2C Master/Slave General Configuration

      1266
  • 39.3 I2C Controller Transfers

    1266
    • Figure 39-3. I2C Transfer Timing

      1267
    • 39.3.1 I2C Master Write (Slave Read)

      1267
      • Figure 39-4. I2C Master Write Timing

        1267
    • 39.3.2 I2C Loopback Testing

      1268
    • 39.3.3 I2C Master Read (Slave Write)

      1268
      • Figure 39-5. I2C Master Read Timing

        1268
    • 39.3.4 I2C Multi-Master Considerations

      1269
  • 39.4 I2C Registers

    1270
    • 39.4.1 I2C Mode Register (I2MOD)

      1270
      • Figure 39-6. I2C Mode Register (I2MOD)

        1270
      • Table 39-1. II2MOD Field Descriptions

        1270
    • 39.4.2 I2C Address Register (I2ADD)

      1270
      • Figure 39-7. I2C Address Register (I2ADD)

        1271
      • Table 39-2. I2ADD Field Descriptions

        1271
    • 39.4.3 I2C Baud Rate Generator Register (I2BRG)

      1271
      • Figure 39-8. I2C Baud Rate Generator Register (I2BRG)

        1271
      • Table 39-3. I2BRG Field Descriptions

        1271
    • 39.4.4 I2C Event/Mask Registers (I2CER/I2CMR)

      1271
      • Figure 39-9. I2C Event/Mask Registers (I2CER/I2CMR)

        1272
      • Table 39-4. I2CER/I2CMR Field Descriptions

        1272
    • 39.4.5 I2C Command Register (I2COM)

      1272
      • Figure 39-10. I2C Command Register (I2COM)

        1272
      • Table 39-5. I2COM Field Descriptions

        1272
  • 39.5 I2C Parameter RAM

    1273
    • Table 39-6. I2C Parameter RAM Memory Map (continued)

      1273
    • Figure 39-11. I2C Function Code Registers (RFCR/TFCR)

      1274
    • Table 39-7. RFCR/TFCR Field Descriptions

      1274
  • 39.6 I2C Commands

    1275
    • Table 39-8. I2C Transmit/Receive Commands

      1275
  • 39.7 The I2C Buffer Descriptor (BD) Table

    1275
    • Figure 39-12. I2C Memory Structure

      1276
    • 39.7.1 I2C Buffer Descriptors (BDs)

      1276
      • 39.7.1.1 I2C Receive Buffer Descriptor (RxBD)

        1276
        • Figure 39-13. I2C RxBD

          1277
        • Table 39-9. I2C RxBD Status and Control Bits

          1277
      • 39.7.1.2 I2C Transmit Buffer Descriptor (TxBD)

        1277
        • Figure 39-14. I2C TxBD

          1278
        • Table 39-10. I2C TxBD Status and Control Bits

          1278
• Chapter 40 Parallel I/O Ports

  1279
  • 40.1 Features

    1279
  • 40.2 Port Registers

    1279
    • 40.2.1 Port Open-Drain Registers (PODRA-PODRD)

      1279
      • Figure 40-1. Port Open-Drain Registers (PODRA-PODRD)

        1280
      • Table 40-1. PODRx Field Descriptions

        1280
    • 40.2.2 Port Data Registers (PDATA-PDATD)

      1280
      • Figure 40-2. Port Data Registers (PDATA-PDATD)

        1281
    • 40.2.3 Port Data Direction Registers (PDIRA-PDIRD)

      1281
      • Figure 40-3. Port Data Direction Register (PDIR)

        1281
      • Table 40-2. PDIR Field Descriptions

        1281
    • 40.2.4 Port Pin Assignment Register (PPAR)

      1282
      • Figure 40-4. Port Pin Assignment Register (PPARA-PPARD)

        1282
      • Table 40-3. PPAR Field Descriptions

        1282
    • 40.2.5 Port Special Options Registers A-D (PSORA-PSORD)

      1282
      • Figure 40-5. Special Options Registers (PSORA-POSRD)

        1283
      • Table 40-4. PSORx Field Descriptions

        1283
  • 40.3 Port Block Diagram

    1283
    • Figure 40-6. Port Functional Operation

      1284
  • 40.4 Port Pins Functions

    1284
    • 40.4.1 General Purpose I/O Pins

      1285
    • 40.4.2 Dedicated Pins

      1285
  • 40.5 Ports Tables

    1285
    • Figure 40-7. Primary and Secondary Option Programming

      1286
    • Table 40-5. Port A-Dedicated Pin Assignment (PPARA = 1) (continued)

      1286
    • Table 40-6. Port B Dedicated Pin Assignment (PPARB = 1) (continued)

      1290
    • Table 40-7. Port C Dedicated Pin Assignment (PPARC = 1) (continued)

      1292
    • Table 40-8. Port D Dedicated Pin Assignment (PPARD = 1) (continued)

      1295
  • 40.6 Interrupts from Port C

    1297
• Appendix A Register Quick Reference Guide

  1299
  • A.1 PowerPC Registers-User Registers

    1299
  • A.2 PowerPC Registers-Supervisor Registers

    1299
  • A.3 MPC8260-Specific SPRs

    1301
• Appendix B Reference Manual (Rev 1) Errata

  1303
  • B.1 Document Errata

    1303
• Glossary

  1319
• Index

  1329