Epson ARM720T Benutzerhandbuch

This chapter provides an introduction to the ARM720T processor. It contains the following 

sections:

The ARM720T processor is a general-purpose 32-bit microprocessor with 8KB cache, enlarged 

write buffer, and 

Memory Management Unit

 (MMU) combined in a single chip. The ARM720T 

processor uses the ARM7TDMI-S CPU, and is software-compatible with the ARM processor 

family.
The on-chip mixed data and instruction cache, together with the write buffer, substantially 

raise the average execution speed and reduce the average amount of memory bandwidth 

required by the processor. This enables the external memory to support additional processors 

or 

Direct Memory Access

 (DMA) channels with minimal performance loss.

The MMU supports a conventional two-level page table structure and several extensions that 

make it ideal for running high-end embedded applications and sophisticated operating 

systems.
The allocation of virtual addresses with different task IDs improves performance in task 

switching operations with the cache enabled. These relocated virtual addresses are monitored 

by the EmbeddedICE-RT block.
The memory interface enables the performance potential to be realized without incurring high 

costs in the memory system. Speed-critical control signals are pipelined to allow system 

control functions to be implemented in standard low-power logic. These control signals permit 

the exploitation of paged mode access offered by industry-standard DRAMs.
The ARM720T processor is provided with an 

Embedded Trace Macrocell

 (ETM) interface that 

brings out the required signals from the ARM core to the periphery of the ARM720T processor. 

This enables you to connect a standard ETM7 macrocell.
The ARM720T processor is a fully static part and has been designed to minimize power 

requirements. This makes it ideal for portable applications where low power consumption is 

essential.
The ARM720T processor architecture is based on 

Reduced Instruction Set Computer

 (RISC) 

principles. The instruction set and related decode mechanism are greatly simplified compared 

with microprogrammed 

Complex Instruction Set Computers

 (CISCs).