Benutzerhandbuch für Epson ARM720T

Inhaltsverzeichnis

• Contents

  5
• Preface

  15
  • About this document

    15
    • Intended audience

      15
    • Using this manual

      15
    • Typographical conventions

      16
    • Product revision status

      16
    • Timing diagram conventions

      17
    • Further reading

      17
      • ARM publications

        17
      • Other publications

        17
• 1 Introduction

  21
  • 1.1 About the ARM720T processor

    21
    • 1.1.1 EmbeddedICE-RT logic

      23
      • Changes to the programmer’s model

        24
  • 1.2 Coprocessors

    25
  • 1.3 About the instruction set

    25
    • 1.3.1 Format summary

      26
    • 1.3.2 ARM instruction set

      27
    • 1.3.3 Thumb instruction set

      34
  • 1.4 Silicon revisions

    38
• 2 Programmer’s Model

  41
  • 2.1 Processor operating states

    41
    • 2.1.1 Switching between processor states

      41
      • Entering Thumb state

        41
      • Entering ARM state

        41
  • 2.2 Memory formats

    42
    • 2.2.1 Big-endian format

      42
    • 2.2.2 Little-endian format

      43
  • 2.3 Instruction length

    43
  • 2.4 Data types

    43
  • 2.5 Operating modes

    44
    • 2.5.1 Changing operating modes

      44
  • 2.6 Registers

    44
    • 2.6.1 The ARM state register set

      44
      • Interrupt modes

        45
    • 2.6.2 The Thumb state register set

      46
    • 2.6.3 The relationship between ARM and Thumb state registers

      47
    • 2.6.4 Accessing high registers in Thumb state

      47
  • 2.7 Program status registers

    48
    • 2.7.1 The condition code flags

      48
    • 2.7.2 The control bits

      48
    • 2.7.3 Reserved bits

      49
  • 2.8 Exceptions

    50
    • 2.8.1 Action on entering an exception

      50
    • 2.8.2 Action on leaving an exception

      51
    • 2.8.3 Exception entry and exit summary

      51
    • 2.8.4 Fast interrupt request

      52
    • 2.8.5 Interrupt request

      52
    • 2.8.6 Abort

      52
    • 2.8.7 Software interrupt

      53
    • 2.8.8 Undefined instruction

      53
    • 2.8.9 Exception vectors

      53
    • 2.8.10 Exception priorities

      54
    • 2.8.11 Exception restrictions

      54
  • 2.9 Relocation of low virtual addresses by the FCSE PID

    55
  • 2.10 Reset

    56
  • 2.11 Implementation-defined behavior of instructions

    57
    • 2.11.1 Indexed addressing on a Data Abort

      57
    • 2.11.2 Early termination

      57
• 3 Configuration

  61
  • 3.1 About configuration

    61
    • 3.1.1 Compatibility

      61
    • 3.1.2 Notation

      61
  • 3.2 Internal coprocessor instructions

    62
  • 3.3 Registers

    63
    • 3.3.1 ID Register

      63
    • 3.3.2 Control Register

      64
      • Enabling the MMU

        65
    • 3.3.3 Translation Table Base Register

      65
    • 3.3.4 Domain Access Control Register

      66
    • 3.3.5 Fault Status Register

      66
    • 3.3.6 Fault Address Register

      67
    • 3.3.7 Cache Operations Register

      67
    • 3.3.8 TLB Operations Register

      67
    • 3.3.9 Process Identifier Registers

      68
      • Fast Context Switch Extension Process Identifier Register

        68
      • Changing FCSE PID

        68
      • Trace Process Identifier Register

        68
    • 3.3.10 Register 14, reserved

      69
    • 3.3.11 Test Register

      69
• 4 Instruction and Data Cache

  73
  • 4.1 About the instruction and data cache

    73
    • 4.1.1 IDC operation

      73
    • 4.1.2 Cachable bit

      73
      • Cachable reads (C=1)

        73
      • Uncachable reads (C=0)

        73
    • 4.1.3 Read-lock-write

      74
  • 4.2 IDC validity

    74
    • 4.2.1 Software IDC flush

      74
    • 4.2.2 Doubly-mapped space

      74
  • 4.3 IDC enable, disable, and reset

    74
• 5 Write Buffer

  77
  • 5.1 About the write buffer

    77
    • 5.1.1 Bufferable bit

      77
  • 5.2 Write buffer operation

    78
    • 5.2.1 Bufferable write

      78
    • 5.2.2 Unbufferable write

      78
    • 5.2.3 Read-lock-write

      78
    • 5.2.4 Reading from a noncachable area

      78
    • 5.2.5 Draining the write buffer

      78
    • 5.2.6 Multi-word writes

      78
• 6 The Bus Interface

  81
  • 6.1 About the bus interface

    81
    • 6.1.1 Summary of the AHB transfer mechanism

      81
  • 6.2 Bus interface signals

    83
  • 6.3 Transfer types

    85
  • 6.4 Address and control signals

    87
    • 6.4.1 HADDR[31:0]

      87
    • 6.4.2 HWRITE

      87
    • 6.4.3 HSIZE[2:0]

      87
    • 6.4.4 HBURST[2:0]

      88
    • 6.4.5 HPROT[3:0]

      88
  • 6.5 Slave transfer response signals

    89
    • 6.5.1 HREADY

      89
    • 6.5.2 HRESP[1:0]

      90
  • 6.6 Data buses

    90
    • 6.6.1 HWDATA[31:0]

      90
    • 6.6.2 HRDATA[31:0]

      91
    • 6.6.3 Endianness

      91
  • 6.7 Arbitration

    92
    • 6.7.1 HBUSREQ

      92
    • 6.7.2 HLOCK

      92
    • 6.7.3 HGRANT

      92
  • 6.8 Bus clocking

    93
    • 6.8.1 HCLK

      93
    • 6.8.2 HCLKEN

      93
  • 6.9 Reset

    93
• 7 Memory Management Unit

  97
  • 7.1 About the MMU

    97
    • 7.1.1 Access permissions and domains

      98
    • 7.1.2 Translated entries

      98
  • 7.2 MMU program-accessible registers

    99
  • 7.3 Address translation

    100
    • 7.3.1 Translation Table Base Register

      100
    • 7.3.2 Level one fetch

      102
    • 7.3.3 Level one descriptor

      102
    • 7.3.4 Section descriptor

      104
    • 7.3.5 Coarse page table descriptor

      104
    • 7.3.6 Fine page table descriptor

      105
    • 7.3.7 Translating section references

      106
    • 7.3.8 Level two descriptor

      106
    • 7.3.9 Translating large page references

      108
    • 7.3.10 Translating small page references

      109
    • 7.3.11 Translating tiny page references

      110
    • 7.3.12 Subpages

      110
  • 7.4 MMU faults and CPU aborts

    111
  • 7.5 Fault address and fault status registers

    112
    • 7.5.1 Fault Status

      112
  • 7.6 Domain access control

    113
  • 7.7 Fault checking sequence

    115
    • 7.7.1 Alignment fault

      115
    • 7.7.2 Translation fault

      116
    • 7.7.3 Domain fault

      116
    • 7.7.4 Permission fault

      116
  • 7.8 External aborts

    117
  • 7.9 Interaction of the MMU and cache

    117
    • 7.9.1 Enabling the MMU

      117
    • 7.9.2 Disabling the MMU

      117
• 8 Coprocessor Interface

  121
  • 8.1 About coprocessors

    121
    • 8.1.1 Coprocessor availability

      122
  • 8.2 Coprocessor interface signals

    123
  • 8.3 Pipeline-following signals

    124
  • 8.4 Coprocessor interface handshaking

    125
    • 8.4.1 The coprocessor

      125
    • 8.4.2 The ARM720T core

      125
    • 8.4.3 Coprocessor signaling

      126
    • 8.4.4 Consequences of busywaiting

      126
    • 8.4.5 Coprocessor register transfer instructions

      127
    • 8.4.6 Coprocessor data operations

      127
    • 8.4.7 Coprocessor load and store operations

      128
  • 8.5 Connecting coprocessors

    129
    • 8.5.1 Connecting a single coprocessor

      129
    • 8.5.2 Connecting multiple coprocessors

      129
  • 8.6 Not using an external coprocessor

    130
  • 8.7 STC operations

    130
  • 8.8 Undefined instructions

    130
  • 8.9 Privileged instructions

    130
• 9 Debugging Your System

  133
  • 9.1 About debugging your system

    134
    • 9.1.1 A typical debug system

      134
  • 9.2 Controlling debugging

    135
    • 9.2.1 Debug modes

      136
    • 9.2.2 Examining system state during debugging

      136
  • 9.3 Entry into debug state

    137
    • 9.3.1 Entry into debug state on breakpoint

      138
    • 9.3.2 Entry into debug state on watchpoint

      138
    • 9.3.3 Entry into debug state on debug request

      139
    • 9.3.4 Action of the ARM720T processor in debug state

      139
    • 9.3.5 Clocks

      140
  • 9.4 Debug interface

    141
    • 9.4.1 Debug interface signals

      141
  • 9.5 ARM720T core clock domains

    141
  • 9.6 The EmbeddedICE-RT macrocell

    142
  • 9.7 Disabling EmbeddedICE-RT

    143
  • 9.8 EmbeddedICE-RT register map

    144
  • 9.9 Monitor mode debugging

    144
    • 9.9.1 Enabling monitor mode

      144
    • 9.9.2 Restrictions on monitor-mode debugging

      145
  • 9.10 The debug communications channel

    146
    • 9.10.1 Domain Access Control Register

      146
      • Instructions

        147
    • 9.10.2 Communications through the DCC

      148
      • Sending a message to the debugger

        148
      • Receiving a message from the debugger

        148
  • 9.11 Scan chains and the JTAG interface

    149
    • 9.11.1 Scan chain implementation

      149
      • Scan chain 1

        149
      • Scan chain 2

        149
      • Scan chain 15

        150
    • 9.11.2 Controlling the JTAG interface

      150
  • 9.12 The TAP controller

    151
    • 9.12.1 Resetting the TAP controller

      151
  • 9.13 Public JTAG instructions

    152
    • 9.13.1 SCAN_N (b0010)

      152
    • 9.13.2 INTEST (b1100)

      152
    • 9.13.3 IDCODE (b1110)

      153
    • 9.13.4 BYPASS (b1111)

      153
    • 9.13.5 RESTART (b0100)

      153
  • 9.14 Test data registers

    154
    • 9.14.1 Bypass register

      154
    • 9.14.2 ARM720T processor device identification (ID) code register

      154
    • 9.14.3 Instruction register

      155
    • 9.14.4 Scan path select register

      155
    • 9.14.5 Scan chains 1 and 2

      156
      • Scan chain 1

        156
      • Scan chain 2

        156
  • 9.15 Scan timing

    157
    • 9.15.1 Scan chain 1 cells

      157
  • 9.16 Examining the core and the system in debug state

    158
    • 9.16.1 Determining the core state

      159
    • 9.16.2 Determining system state

      160
  • 9.17 Exit from debug state

    161
  • 9.18 The program counter during debug

    162
    • 9.18.1 Breakpoints

      162
    • 9.18.2 Watchpoints

      162
    • 9.18.3 Watchpoint with another exception

      163
    • 9.18.4 Debug request

      163
    • 9.18.5 System speed access

      163
    • 9.18.6 Summary of return address calculations

      164
  • 9.19 Priorities and exceptions

    164
    • 9.19.1 Breakpoint with Prefetch Abort

      164
    • 9.19.2 Interrupts

      165
    • 9.19.3 Data Aborts

      165
  • 9.20 Watchpoint unit registers

    165
    • 9.20.1 Programming and reading watchpoint registers

      165
    • 9.20.2 Using the data, and address mask registers

      167
    • 9.20.3 The watchpoint unit control registers

      167
  • 9.21 Programming breakpoints

    168
    • 9.21.1 Hardware breakpoints

      168
    • 9.21.2 Software breakpoints

      169
      • Setting the breakpoint

        169
      • Clearing the breakpoint

        169
  • 9.22 Programming watchpoints

    170
  • 9.23 Abort status register

    170
  • 9.24 Debug control register

    171
    • 9.24.1 Disabling interrupts

      172
    • 9.24.2 Forcing DBGRQ

      172
    • 9.24.3 Forcing DBGACK

      172
  • 9.25 Debug status register

    173
  • 9.26 Coupling breakpoints and watchpoints

    175
    • 9.26.1 Breakpoint and watchpoint coupling example

      175
      • CHAINOUT signal

        175
    • 9.26.2 DBGRNG signal

      176
  • 9.27 EmbeddedICE-RT timing

    176
• 10 ETM Interface

  179
  • 10.1 About the ETM interface

    179
  • 10.2 Enabling and disabling the ETM7 interface

    179
  • 10.3 Connections between the ETM7 macrocell and the ARM720T processor

    180
  • 10.4 Clocks and resets

    181
  • 10.5 Debug request wiring

    181
  • 10.6 TAP interface wiring

    181
• 11 Test Support

  185
  • 11.1 About the ARM720T test registers

    185
  • 11.2 Automatic Test Pattern Generation (ATPG)

    186
    • 11.2.1 ARM720T processor INTEST/EXTEST wrapper

      186
      • ATPG

        186
  • 11.3 Test State Register

    187
  • 11.4 Cache test registers and operations

    187
    • 11.4.1 Addressing the CAM and RAM

      190
  • 11.5 MMU test registers and operations

    192
    • 11.5.1 Addressing the CAM, RAM1, and RAM2

      196
  • A.1 AMBA interface signals

    201
  • A.2 Coprocessor interface signals

    202
  • A.3 JTAG and test signals

    203
  • A.4 Debugger signals

    204
  • A.5 Embedded trace macrocell interface signals

    205
  • A.6 ATPG test signals

    207
  • A.7 Miscellaneous signals

    207
• Appendix A Signal Descriptions

  201
• Glossary

  211
• Index

  219