Epson ARM720T Benutzerhandbuch
2: Programmer’s Model
2-6
EPSON
ARM720T CORE CPU MANUAL
2.6.2
The Thumb state register set
The Thumb state register set is a subset of the ARM state set. You have direct access to:
•
eight general registers, (r0–r7)
•
the PC
•
a
Stack Pointer
(SP)
register
•
a
Link Register
(LR)
•
the CPSR.
There are banked SPs, LRs, and
Saved Program Status Registers
(SPSRs) for each privileged
mode. This is shown in Figure 2-4.
Figure 2-4 Register organization in Thumb state
Thumb state general registers and program counter
System and User
r0
r1
r2
r3
r4
r5
r6
r7
SP
LR
PC
CPSR
CPSR
SPSR_fiq
CPSR
SPSR_svc
CPSR
SPSR_abt
CPSR
SPSR_irq
CPSR
SPSR_und
Thumb state program status registers
= banked register
FIQ
r0
r1
r2
r3
r4
r5
r6
r7
SP_fiq
LR_fiq
PC
Supervisor
r0
r1
r2
r3
r4
r5
r6
r7
SP_svc
LR_svc
PC
Abort
r0
r1
r2
r3
r4
r5
r6
r7
SP_abt
LR_abt
PC
IRQ
r0
r1
r2
r3
r4
r5
r6
r7
SP_irq
LR_irq
PC
Undefined
r0
r1
r2
r3
r4
r5
r6
r7
SP_und
LR_und
PC