Epson ARM720T Benutzerhandbuch

Exceptions arise whenever the normal flow of a program has to be halted temporarily, for 

example to service an interrupt from a peripheral. Before an exception can be handled, the 

current processor state is preserved so that the original program can resume when the handler 

routine has finished.
Several exceptions can arise at the same time. If this happens, they are dealt with in a fixed 

order. See 

Exception behavior is described in the following sections:

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When handling an exception, the ARM720T processor behaves as follows: 

1

It preserves the address of the next instruction in the appropriate LR.
a.

If the exception has been entered from ARM state, the address of the next 

instruction is copied into the LR (that is, current PC+4 or PC+8 depending on 

the exception). See Table 2-3 on page 2-11 for details).

b.

If the exception has been entered from Thumb state, the value written into the 

LR is the current PC, offset by a value so that the program resumes from the 

correct place on return from the exception. This means that the exception 

handler does not have to determine which state the exception was entered 

from. 

For example, in the case of SWI:
MOVS PC, r14_svc 
always returns to the next instruction regardless of whether the SWI was executed 

in ARM or Thumb state.

2

It copies the CPSR into the appropriate SPSR.

3

It forces the CPSR mode bits to a value that depends on the exception.

4

It forces the PC to fetch the next instruction from the relevant exception vector.

It can also set the interrupt disable flags to prevent otherwise unmanageable nestings of 

exceptions.
If the processor is in Thumb state when an exception occurs, it automatically switches into 

ARM state when the PC is loaded with the exception vector address.