Epson ARM720T Benutzerhandbuch

Epson

CONTENTS

ii EPSON ARM720T CORE CPU MANUAL

Reset ....................................................................................................... 6-13

Memory Management Unit

About the MMU.......................................................................................... 7-1

MMU program-accessible registers ........................................................... 7-3

Address translation .................................................................................... 7-4

MMU faults and CPU aborts .................................................................... 7-15

Fault address and fault status registers................................................... 7-16

Domain access control ............................................................................ 7-17

Fault checking sequence ......................................................................... 7-19

External aborts......................................................................................... 7-21

Interaction of the MMU and cache........................................................... 7-21

Coprocessor Interface

About coprocessors ................................................................................... 8-1

Coprocessor interface signals ................................................................... 8-3

Pipeline-following signals........................................................................... 8-4

Coprocessor interface handshaking .......................................................... 8-5

Connecting coprocessors .......................................................................... 8-9

Not using an external coprocessor .......................................................... 8-10

STC operations........................................................................................ 8-10

Undefined instructions ............................................................................. 8-10

Privileged instructions.............................................................................. 8-10

Debugging Your System

About debugging your system ................................................................... 9-2

Controlling debugging................................................................................ 9-3

Entry into debug state................................................................................ 9-5

Debug interface ......................................................................................... 9-9

ARM720T core clock domains................................................................... 9-9

The EmbeddedICE-RT macrocell............................................................ 9-10

Disabling EmbeddedICE-RT.................................................................... 9-11

EmbeddedICE-RT register map .............................................................. 9-12

Monitor mode debugging ......................................................................... 9-12

The debug communications channel ....................................................... 9-14

Scan chains and the JTAG interface ....................................................... 9-17

The TAP controller................................................................................... 9-19

Public JTAG instructions.......................................................................... 9-20

Test data registers ................................................................................... 9-22

Scan timing .............................................................................................. 9-25

Examining the core and the system in debug state ................................. 9-26

Exit from debug state............................................................................... 9-29

The program counter during debug ......................................................... 9-30

Priorities and exceptions.......................................................................... 9-32

Watchpoint unit registers ......................................................................... 9-33

Programming breakpoints........................................................................ 9-36

Programming watchpoints ....................................................................... 9-38

Abort status register................................................................................. 9-38

Debug control register ............................................................................. 9-39

Debug status register............................................................................... 9-41

Coupling breakpoints and watchpoints .................................................... 9-43

EmbeddedICE-RT timing......................................................................... 9-44