Texas Instruments TMS320C64x DSP Benutzerhandbuch
Figures
xi
Figures
SPRU629
Figures
1–1
Video Port Block Diagram
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1–2
BT.656 Video Capture FIFO Configuration
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1–3
8/10-Bit Raw Video Capture and TSI Video Capture FIFO Configuration
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1–4
Y/C Video Capture FIFO Configuration
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1–5
16/20-Bit Raw Video Capture FIFO Configuration
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1–6
BT.656 Video Display FIFO Configuration
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1–7
8/10-Bit Raw Video Display FIFO Configuration
1–8
8/10 Bit Locked Raw Video Display FIFO Configuration
1–9
16/20-Bit Raw Video Display FIFO Configuration
1–10
Y/C Video Display FIFO Configuration
2–1
Capture DMA Event Generation Flow Diagram
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2–2
Display DMA Event Generation Flow Diagram
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2–3
Video Port Control Register (VPCTL)
2–4
Video Port Status Register (VPSTAT)
2–5
Video Port Interrupt Enable Register (VPIE)
2–6
Video Port Interrupt Status Register (VPIS)
3–1
Video Capture Parameters
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3–2
8-Bit BT.656 FIFO Packing
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3–3
10-Bit BT.656 FIFO Packing
3–4
10-Bit BT.656 Dense FIFO Packing
3–5
8-Bit Y/C FIFO Packing
3–6
10-Bit Y/C FIFO Packing
3–7
10-Bit Y/C Dense FIFO Packing
3–8
VCOUNT Operation Example (EXC = 0)
3–9
HCOUNT Operation Example (EXC = 0)
3–10
HCOUNT Operation Example (EXC = 1)
3–11
Field 1 Detection Timing
3–12
Chrominance Resampling
3–13
1/2 Scaled Co-Sited Filtering
3–14
1/2 Scaled Chrominance Resampled Filtering
3–15
Edge Pixel Replication
3–16
Capture Window Not Requiring Edge Pixel Replication
3–17
8-Bit Raw Data FIFO Packing
3–18
10-Bit Raw Data FIFO Packing
3–19
10-Bit Dense Raw Data FIFO Packing
3–20
16-Bit Raw Data FIFO Packing