Texas Instruments TMS320C64x DSP Benutzerhandbuch
Video Capture Registers
Video Capture Port
3-58
SPRU629
3.13.3 Video Capture Channel x Field 1 Start Register (VCASTRT1, VCBSTRT1)
The captured image is a subset of the incoming image. The video capture
channel x field 1 start register (VCASTRT1, VCBSTRT1) defines the start of
the field 1 captured image. Note that the size is defined relative to incoming
data (before scaling). VCxSTRT1 is shown in Figure 3–31 and described in
Table 3–16.
channel x field 1 start register (VCASTRT1, VCBSTRT1) defines the start of
the field 1 captured image. Note that the size is defined relative to incoming
data (before scaling). VCxSTRT1 is shown in Figure 3–31 and described in
Table 3–16.
In BT.656 or Y/C modes, the horizontal (pixel) counter is reset (to 0) by the hori-
zontal event (as selected by the HRST bit in VCxCTL) and the vertical (line)
counter is reset (to 1) by the vertical event (as selected by the VRST bit in
VCxCTL). Field 1 capture starts when HCOUNT
zontal event (as selected by the HRST bit in VCxCTL) and the vertical (line)
counter is reset (to 1) by the vertical event (as selected by the VRST bit in
VCxCTL). Field 1 capture starts when HCOUNT
=
VCXSTART,
VCOUNT = VCYSTART, and field 1 capture is enabled.
In raw capture mode, the VCVBLNKP bits defines the minimum vertical blank-
ing period. If CAPEN stays deasserted longer than VCVBLNKP clocks, then
a vertical blanking interval is considered to have occurred. If the SSE bit is set
when the capture first begins (the VCEN bit is set in VCxCTL), the capture
does not start until two intervals are counted. This allows the video port to syn-
chronize its capture to the top of a frame when first started.
ing period. If CAPEN stays deasserted longer than VCVBLNKP clocks, then
a vertical blanking interval is considered to have occurred. If the SSE bit is set
when the capture first begins (the VCEN bit is set in VCxCTL), the capture
does not start until two intervals are counted. This allows the video port to syn-
chronize its capture to the top of a frame when first started.
In TSI capture mode, the capture starts when the CAPEN signal is asserted,
the FRMC bit (in VCxSTAT) is cleared, and a SYNC byte is detected.
the FRMC bit (in VCxSTAT) is cleared, and a SYNC byte is detected.
Figure 3–31. Video Capture Channel x Field 1 Start Register (VCASTRT1, VCBSTRT1)
31
28
27
16
Reserved
VCYSTART
R-0
R/W-0
15
14
12
11
0
SSE
Reserved
VCXSTART/VCVBLNKP
R/W-1
R-0
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset