Texas Instruments TMS320C64x DSP Benutzerhandbuch
Video Display Mode Selection
Video Display Port
4-8
SPRU629
4.1.4
External Sync Operation
The video display module may be synchronized with an external video source
using external sync signals. VCTL1 may be configured as an external horizon-
tal sync input. When the external HSYNC is asserted, FPCOUNT is loaded
with the HRLD value and VCCOUNT is loaded with the CRLD value. VCTL2
may be configured as an external vertical sync input. When the external
VSYNC is asserted during field 1, FLCOUNT is loaded with the VRLD value.
Field determination is made using either VCTL3 as an external FLD input or
by field detect logic using the VSYNC and HSYNC inputs.
using external sync signals. VCTL1 may be configured as an external horizon-
tal sync input. When the external HSYNC is asserted, FPCOUNT is loaded
with the HRLD value and VCCOUNT is loaded with the CRLD value. VCTL2
may be configured as an external vertical sync input. When the external
VSYNC is asserted during field 1, FLCOUNT is loaded with the VRLD value.
Field determination is made using either VCTL3 as an external FLD input or
by field detect logic using the VSYNC and HSYNC inputs.
4.1.5
Port Sync Operation
The video display module may be synchronized with the video display module
of another video port on the device. This mode is provided to enable the output
of 24-bit or 30-bit RGB data. (for example, 8 bits of R and 8 bits of G on video
port 0 operating in dual-channel synced 8-bit raw mode, and 8 bits of B on
video port 1 operating in 8-bit raw mode with VP1 synced to VP0.) The slave
port must have the same VCLKIN and programmed register values as the
master port. The master port provides the control signals necessary to reset
the slave port counters so that they maintain synchronization. Each video port
may only synchronize to the previous video port (the one with a lower number).
An example for a three port device is shown in Figure 4–7.
of another video port on the device. This mode is provided to enable the output
of 24-bit or 30-bit RGB data. (for example, 8 bits of R and 8 bits of G on video
port 0 operating in dual-channel synced 8-bit raw mode, and 8 bits of B on
video port 1 operating in 8-bit raw mode with VP1 synced to VP0.) The slave
port must have the same VCLKIN and programmed register values as the
master port. The master port provides the control signals necessary to reset
the slave port counters so that they maintain synchronization. Each video port
may only synchronize to the previous video port (the one with a lower number).
An example for a three port device is shown in Figure 4–7.
Figure 4–7. Video Display Module Synchronization Chain
Video port 0
display
Can sync to
Video port 1
display
Can sync to
Video port 2
display