Texas Instruments TMS320C64x DSP Benutzerhandbuch
BT.656 Video Display Mode
Video Display Port
4-12
SPRU629
4.2.2
Blanking Codes
The time between the EAV and SAV code on each line represents the horizontal
blanking interval. During this time, the video port outputs digital video blanking
values. These values are 10.0h for luma (Y) samples and 80.0h for chroma
(Cb/Cr) samples. These values are also output during the active line period of
vertical blanking (between SAV and EAV when V = 1). In addition, if the DVEN
bit in VDCTL is cleared to 0, the blanking values are output during the portion
of active video lines that are not a part of the displayed image.
blanking interval. During this time, the video port outputs digital video blanking
values. These values are 10.0h for luma (Y) samples and 80.0h for chroma
(Cb/Cr) samples. These values are also output during the active line period of
vertical blanking (between SAV and EAV when V = 1). In addition, if the DVEN
bit in VDCTL is cleared to 0, the blanking values are output during the portion
of active video lines that are not a part of the displayed image.
4.2.3
BT.656 Image Display
For BT.656 display mode, the FIFO buffer is divided into three sections. One
FIFO is 2560-bytes deep and is used for the storage of Y output samples; the
other two FIFOs are each 1280-bytes deep and are dedicated for storage of
Cb and Cr samples. Each FIFO has a memory-mapped location associated
with it; YDST, CBDST, and CRDST. The pseudo-registers are write-only and
are used by DMAs to fill the FIFOs with output data. The video display module
multiplexes the data from the three FIFOs to generate the output CbYCrY data
stream.
FIFO is 2560-bytes deep and is used for the storage of Y output samples; the
other two FIFOs are each 1280-bytes deep and are dedicated for storage of
Cb and Cr samples. Each FIFO has a memory-mapped location associated
with it; YDST, CBDST, and CRDST. The pseudo-registers are write-only and
are used by DMAs to fill the FIFOs with output data. The video display module
multiplexes the data from the three FIFOs to generate the output CbYCrY data
stream.
If video display is enabled, the video display module uses the YEVT, CbEVT,
and CrEVT events to notify the DMA controller that data needs to be placed
into the display FIFOs. The number of pixels required to generate the events
is set by the VDTHRLD bits in VDTHRLD (VTHRLD must be an even number).
The video display module generates the event signals when the display buffer
holds less than the VDTHRLD number of pixels and the DEVTCT counter has
not expired. On every YEVT, the DMA should move data from DSP memory
to the Y buffer, using the Y FIFO destination register (YDST) content as the
destination address. On every CbEVT, the DMA should move data from DSP
memory to the Cb buffer, using the Cb FIFO destination register (CBDST)
content as the destination address. On every CrEVT, the DMA should move
data from DSP memory to the Cr buffer, using the Cr FIFO destination register
(CRDST) content as the destination address. The DMA transfer size for the
Y buffer is twice the size of the DMA for the Cb or Cr buffers.
and CrEVT events to notify the DMA controller that data needs to be placed
into the display FIFOs. The number of pixels required to generate the events
is set by the VDTHRLD bits in VDTHRLD (VTHRLD must be an even number).
The video display module generates the event signals when the display buffer
holds less than the VDTHRLD number of pixels and the DEVTCT counter has
not expired. On every YEVT, the DMA should move data from DSP memory
to the Y buffer, using the Y FIFO destination register (YDST) content as the
destination address. On every CbEVT, the DMA should move data from DSP
memory to the Cb buffer, using the Cb FIFO destination register (CBDST)
content as the destination address. On every CrEVT, the DMA should move
data from DSP memory to the Cr buffer, using the Cr FIFO destination register
(CRDST) content as the destination address. The DMA transfer size for the
Y buffer is twice the size of the DMA for the Cb or Cr buffers.