Texas Instruments TMS320C64x DSP Benutzerhandbuch

4-32

1

0

1

0

Continuous field 2 display. Display only field 2. F2D is set after field 2
display and causes DCMPx to be set (DCMPx interrupt can be dis-
abled). No DCNA interrupt occurs, regardless of the state of F2D.

1

0

1

1

Reserved

1

1

0

0

Continuous frame display. Display both fields. FRMD is set after field 2
display and causes DCMPx to be set (DCMPx interrupt can be dis-
abled. No DCNA interrupt occurs, regardless of the state of FRMD.

1

1

0

1

Continuous progressive frame display. Display field 1. FRMD is set af-
ter field 1 display and causes DCMPx to be set (DCMPx interrupt can
be disabled). No DCNA interrupt occurs, regardless of the state of
FRMD. (Functions identically to continuous field 1 display mode except
the FRMD bit is used instead of the F1D bit.) If external control signals
are used, they must follow progressive format.

1

1

1

0

Reserved

1

1

1

1

Reserved

The display FIFOs are filled using DMAs as requested by the video port DMA
events. The VDTHRLD value indicates the level at which the FIFO has enough
room to receive another DMA block of data. Depending on the size of the DMA,
the FIFO may have room for multiple transfers before reaching the VDTHRLD
level. Once the threshold is reached, another DMA event is generated as soon
as the FIFO again falls below the VDTHRLD level.

Once an entire field worth of data has been sent to the FIFO, the video port
may need to stop generating events in order to allow the DSP to change DMA.
Since display may not yet be complete (the FIFO continues to empty after
falling below VDTHRLD), a display event counter (DEVTCT) is provided to
track the number of requested YEVT events. The counter is loaded with the
number of events needed in a display field (DISPEVT1 or DISPEVT2) and is
decremented each time the event is requested. Once the counter reaches 0,
further display events are inhibited. At the start of the next field, DEVTCT is
reloaded and display events are reenabled.