Texas Instruments TMS320C64x DSP Benutzerhandbuch

4-68

†

†

31–28

Reserved

–

0

Reserved. The reserved bit location is always read as
0. A value written to this field has no effect.

27–16

VBLNKYSTOP2

OF(value)

0–FFFh

Specifies the line (in
FLCOUNT) where
VBLNK inactive edge
occurs for field 2. Does
not affect EAV/SAV V bit
operation.

Specifies the line (in
FLCOUNT) where vertical
blanking ends (VBLNK
inactive edge) for field 2.

15–12

Reserved

–

0

Reserved. The reserved bit location is always read as
0. A value written to this field has no effect.

11–0

VBLNKXSTOP2

OF(value)

0–FFFh

Specifies the pixel (in
FPCOUNT) where
VBLNK inactive edge
occurs for field 2.

Specifies the pixel (in
FPCOUNT) where
vertical blanking ends
(VBLNK inactive edge)
for field 2.

† For CSL implementation, use the notation VP_VDVBLKE2_field_symval

The video display field 1 image offset register (VDIMGOFF1) defines the
field 1 image offset and specifies the starting location of the displayed image
relative to the start of the active display. The VDIMGOFF1 is shown in
Figure 4–47 and described in Table 4–14.

The image line counter (ILCOUNT) is reset to 1 on the first image line (when
FLCOUNT = VBLNKYSTOP1 + IMGVOFF1). If the NV bit is set, ILCOUNT is
reset to 1 when FLCOUNT = VBLNKYSTOP1 – IMGVOFF1. Display image
pixels are output in field 1 beginning on the line where ILCOUNT = 1. The
default output values or blanking values are output during active lines prior to
ILCOUNT = 1. For a negative offset, IMGVOFF1 must not be greater than
VBLNKYSTOP1. The field 1 active image must not overlap the field 2 active image.

The image pixel counter (IPCOUNT) is reset to 0 at the start of an active line
image. Once ILCOUNT = 1, image pixels from the FIFO are output on each
line in field 1 beginning when FPCOUNT = IMGHOFF1. If the NH bit is set,
IPCOUNT is reset when FPCOUNT = FRMWIDTH – IMGHOFF1. The default
output values or blanking values are output during active pixels prior to
IMGHOFF1.