Texas Instruments TMS320C64x DSP Benutzerhandbuch

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Video Display Registers
4-71
Video Display Port
SPRU629
4.12.11
Video Display Field 2 Image Offset Register (VDIMGOFF2)
The video display field 2 image offset register (VDIMGOFF2) defines the
field 2 image offset and specifies the starting location of the displayed image
relative to the start of the active display. The VDIMGOFF2 is shown in
Figure 4–49 and described in Table 4–16.
The image line counter (ILCOUNT) is reset to 1 on the first image line (when
FLCOUNT = VBLNKYSTOP2 IMGVOFF2). If the NV bit is set, ILCOUNT is
reset to 1 when FLCOUNT = VBLNKYSTOP2 – IMGVOFF2. Display image
pixels are output in field 2 beginning on the line where ILCOUNT = 1. The
default output values or blanking values are output during active lines prior to
ILCOUNT = 1. For a negative offset, IMGVOFF2 must not be greater than
VBLNKYSTOP2. The field 2 active image must not overlap the field 2 active image.
The image pixel counter (IPCOUNT) is reset to 0 at the start of an active line
image. Once ILCOUNT = 1, image pixels from the FIFO are output on each
line in field 2 beginning when FPCOUNT = IMGHOFF2. If the NH bit is set,
IPCOUNT is reset when FPCOUNT = FRMWIDTH – IMGHOFF2. The default
output values or blanking values are output during active pixels prior to
IMGHOFF2.
Figure 4–49. Video Display Field 2 Image Offset Register (VDIMGOFF2)
31
30
28
27
16
NV
Reserved
IMGVOFF2
R/W-0
R-0
R/W-0
15
14
12
11
0
NH
Reserved
IMGHOFF2
R/W-0
R-0
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset