Texas Instruments TMS320C64x DSP Benutzerhandbuch
Video Display Registers
4-89
Video Display Port
SPRU629
4.12.26
Video Display Field Bit Register (VDFBIT)
The video display field bit register (VDFBIT) controls the F bit value in the EAV
and SAV timing control codes. The VDFBIT is shown in Figure 4–65 and
described in Table 4–31.
and SAV timing control codes. The VDFBIT is shown in Figure 4–65 and
described in Table 4–31.
The FBITCLR and FBITSET bits control the F bit value in the EAV and SAV
timing control codes. The F bit is cleared to 0 (indicating field 1 display) in the
EAV code at the beginning of the line whenever the frame line counter (FLCOUNT)
is equal to FBITCLR. It remains a 0 for all subsequent EAV/SAV codes until
the EAV at the beginning of the line when FLCOUNT = FBITSET where it
changes to 1 (indicating field 2 display). The F bit operation is completely inde-
pendent of the FLD control signal.
timing control codes. The F bit is cleared to 0 (indicating field 1 display) in the
EAV code at the beginning of the line whenever the frame line counter (FLCOUNT)
is equal to FBITCLR. It remains a 0 for all subsequent EAV/SAV codes until
the EAV at the beginning of the line when FLCOUNT = FBITSET where it
changes to 1 (indicating field 2 display). The F bit operation is completely inde-
pendent of the FLD control signal.
For interlaced operation, FBITCLR and FBITSET are typically programmed
such that the F bit changes coincidently with or some time after the V bit transi-
tions from 1 to 0 (as determined by VBITCLR1 and VBITCLR2 in VDVBITn).
For progressive scan operation no field 2 output occurs, so FBITSET should
be programmed to a value greater than FRMHEIGHT so that the condition
FLCOUNT = FBITSET never occurs and the F bit is always 0.
such that the F bit changes coincidently with or some time after the V bit transi-
tions from 1 to 0 (as determined by VBITCLR1 and VBITCLR2 in VDVBITn).
For progressive scan operation no field 2 output occurs, so FBITSET should
be programmed to a value greater than FRMHEIGHT so that the condition
FLCOUNT = FBITSET never occurs and the F bit is always 0.
Figure 4–65. Video Display Field Bit Register (VDFBIT)
31
28
27
16
Reserved
FBITSET
R-0
R/W-0
15
12
11
0
Reserved
FBITCLR
R-0
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 4–31. Video Display Field Bit Register (VDFBIT) Field Descriptions
Description
Bit
field
†
symval
†
Value
BT.656 and Y/C Mode
Raw Data Mode
31–28
Reserved
–
0
Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
value written to this field has no effect.
27–16
FBITSET
OF(value)
0–FFFh
Specifies the first line with an EAV of
F = 1 indicating field 2 display.
F = 1 indicating field 2 display.
Not used.
15–12
Reserved
–
0
Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
value written to this field has no effect.
11–0
FBITCLR
OF(value)
0–FFFh
Specifies the first line with an EAV of
F = 0 indicating field 1 display.
F = 0 indicating field 1 display.
Not used.
† For CSL implementation, use the notation VP_VDFBIT_field_symval