Texas Instruments TMS320C64x DSP Benutzerhandbuch
Video Display Registers
Video Display Port
4-92
SPRU629
4.12.28
Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2)
The video display field 2 vertical blanking bit register (VDVBIT2) controls the
V bit in the EAV and SAV timing control words for field 2. The VDVBIT2 is
shown in Figure 4–67 and described in Table 4–33.
V bit in the EAV and SAV timing control words for field 2. The VDVBIT2 is
shown in Figure 4–67 and described in Table 4–33.
The VBITSET2 and VBITCLR2 bits control the V bit value in the EAV and SAV
timing control codes. The V bit is set to 1 (indicating the start of field 2 digital
vertical blanking) in the EAV code at the beginning of the line whenever the
frame line counter (FLCOUNT) is equal to VBITSET2. It remains a 1 for all
EAV/SAV codes until the EAV at the beginning of the line on when
FLCOUNT = VBITCLR2 where it changes to 0 (indicating the start of the
field 2 digital active display). The V bit operation is completely independent of
the VBLNK control signal.
timing control codes. The V bit is set to 1 (indicating the start of field 2 digital
vertical blanking) in the EAV code at the beginning of the line whenever the
frame line counter (FLCOUNT) is equal to VBITSET2. It remains a 1 for all
EAV/SAV codes until the EAV at the beginning of the line on when
FLCOUNT = VBITCLR2 where it changes to 0 (indicating the start of the
field 2 digital active display). The V bit operation is completely independent of
the VBLNK control signal.
For correct interlaced operation, the region defined by VBITSET2 and
VBITCLR2 must not overlap the region defined by VBITSET1 and VBITCLR1.
For progressive scan operation, VBITSET2 and VBITCLR2 should be
programmed to a value greater than FRMHEIGHT.
VBITCLR2 must not overlap the region defined by VBITSET1 and VBITCLR1.
For progressive scan operation, VBITSET2 and VBITCLR2 should be
programmed to a value greater than FRMHEIGHT.
Figure 4–67. Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2)
31
28
27
16
Reserved
VBITCLR2
R-0
R/W-0
15
12
11
0
Reserved
VBITSET2
R-0
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset