Texas Instruments TMS320C64x DSP Benutzerhandbuch
GPIO Registers
5-25
General Purpose I/O Operation
SPRU629
5.1.12 Video Port Pin Interrupt Clear Register (PICLR)
The video port pin interrupt clear register (PICLR) is shown in Figure 5–12 and
described in Table 5–13. PICLR is an alias of the video port pin interrupt status
register (PISTAT) for writes only. Writing a 1 to a bit of PICLR clears the corre-
sponding bit in PISTAT. Writing a 0 has no effect. Register reads return all 0s.
described in Table 5–13. PICLR is an alias of the video port pin interrupt status
register (PISTAT) for writes only. Writing a 1 to a bit of PICLR clears the corre-
sponding bit in PISTAT. Writing a 0 has no effect. Register reads return all 0s.
Figure 5–12. Video Port Pin Interrupt Clear Register (PICLR)
31
24
Reserved
R-0
23
22
21
20
19
18
17
16
Reserved
PICLR22
PICLR21
PICLR20
PICLR19
PICLR18
PICLR17
PICLR16
R-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
PICLR15
PICLR14
PICLR13
PICLR12
PICLR11
PICLR10
PICLR9
PICLR8
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
7
6
5
4
3
2
1
0
PICLR7
PICLR6
PICLR5
PICLR4
PICLR3
PICLR2
PICLR1
PICLR0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
Legend: R = Read only; W = Write only; -n = value after reset