Texas Instruments TMS320C64x DSP Benutzerhandbuch

Video Port Pin Mapping

1-13

Overview

SPRU629

1.4

Video Port Pin Mapping

The video port requires 21 external signal pins for full functionality. Pin usage
and direction changes depend on the selected operating mode. Pin functional-
ity detail for video capture mode is listed in Table 1–1. Pin functionality detail
for video display mode is listed in Table 1–2. All unused port signals (except
VCLK1 and VCLK2) can be configured as general-purpose I/O (GPIO) pins.

Table 1–1. Video Capture Signal Mapping

Usage

BT.656 Capture Mode

Raw Data Capture Mode

Video Port

Signal

I/O

Dual

Channel

Single

Channel

Y/C Capture

Mode

8/10-Bit

16/20-Bit

TSI Capture

Mode

VDATA[9–0]

I/O

VDIN[9–0]

(In) Ch A

VDIN[9–0]

(In) Ch A

VDIN[9–0]

(In) (Y)

VDIN[9–0]

(In) Ch A

VDIN[9–0]

(In)

VDIN[7–0]

(In)

VDATA[19–10]

I/O

VDIN[19–10]

(In) Ch B

Not Used

VDIN[19–10]

(In) (Cb/Cr)

VDIN[19–10]

(In) Ch B

VDIN[19–10]

(In)

Not Used

VCLK1 I VCLKINA (In) VCLKINA (In) VCLKINA (In) VCLKINA (In) VCLKINA (In) VCLKINA (In)

VCLK2

I/O

VCLKINB (In)

Not Used

VCLKINB (In)

Not Used

VCTL1

I/O

CAPENA

(In)

CAPENA/

AVID/HSYNC

(In)

CAPENA/

AVID/HSYNC

(In)

CAPENA

(In)

CAPENA

(In)

CAPENA

(In)

VCTL2

I/O

CAPENB

(In)

VBLNK/

VSYNC (In)

VBLNK/

VSYNC (In)

CAPENB

(In)

Not Used

PACSTRT

(In)

VCTL3

I/O

Not Used

FID

(In)

FID

(In)

FID (In)

Ch A

FID (In)

Ch A

PACERR

(In)

Legend: VCLKINA – Channel A capture clock; CAPENA – Channel A capture enable; VCLKINB – Channel B capture clock;

CAPENB – Channel B capture enable; AVID – Active video; HSYNC – Horizontal synchronization; VBLNK – Vertical
blanking; VSYNC – Vertical synchronization; FID – Field identification; PACSTRT – Packet start; PACERR – Packet
error