Texas Instruments TMS320C64x DSP Benutzerhandbuch

2-13

Some low-cost device implementations with narrow video ports width or
restricted to lower video frequency operations may use a reduced FIFO size.
FIFO size does not affect the DMA request mechanism. The selection of 8-bit
or 10-bit port width automatically cuts the FIFO size in half with support for only
a single channel of operation.

Because of the large amount of buffering provided within the video port and
the programmable threshold used to generate DMA events, the required DMA
latency is difficult to calculate. Because video data is real time, the video port’s
external interface may not be stalled so module throughput must be maintained.

In order to maintain throughput during video capture operation, the capture
FIFO must be emptied at a faster rate than it is filled. The time to completely
fill the capture FIFO may be represented by the formula t

F 

+ n(t

H

), where t

F 

is

the time to fill the FIFO with active samples, t

H

 is the horizontal blanking time,

and n is the number of lines of active video that the FIFO can hold. Maximum
throughput requirements for capture occur during HDTV resolution Y/C mode.
The BT.1120 standard (1125 line/60 Hz mode) specifies a line size of 2200 Y
samples (1920 active) and 1100 ea. Cb and Cr samples (960-ea. active) at a
sample rate of 74.25 MHz. This means that the horizontal blanking time is
280/74.25 MHz or 3.77 

µ

s. In Y/C mode, the Y buffer is 2560 bytes and the

Cr/Cb buffers are 1280 bytes each. The number of samples that the buffers
can hold depends on the buffer packing mode as listed in Table 2–2.