Texas Instruments TMS320C64x DSP Benutzerhandbuch
Y/C Video Capture Mode
3-13
Video Capture Port
SPRU629
3.3.3
Y/C Image Window and Capture
The SDTV Y/C format (CCIR601) is an interlaced format consisting of two
fields just like BT.656. HDTV Y/C formats may be interlaced or progressive
scan. For interlaced capture, the capture windows are programmed identically
to BT.656 mode. For progressive scan formats, only field1 is used.
fields just like BT.656. HDTV Y/C formats may be interlaced or progressive
scan. For interlaced capture, the capture windows are programmed identically
to BT.656 mode. For progressive scan formats, only field1 is used.
In Y/C mode, HCOUNT increments on every luma sample period (every
VCLKINA rising edge) for which capture is enabled. Once YCOUNT = VCYSTART,
line capture begins when HCOUNT = VCXSTART. It continues until
HCOUNT = VCXSTOP. A field’s capture is complete when
HCOUNT = VCXSTOP and VCOUNT = VCYSTOP.
VCLKINA rising edge) for which capture is enabled. Once YCOUNT = VCYSTART,
line capture begins when HCOUNT = VCXSTART. It continues until
HCOUNT = VCXSTOP. A field’s capture is complete when
HCOUNT = VCXSTOP and VCOUNT = VCYSTOP.
For the Y/C video capture mode, the FIFO buffer is divided into three sections
(three buffers). One section is 2560 bytes deep and is dedicated for storage
of Y data samples. The other two sections are dedicated for storage of Cb and
Cr data samples, respectively. The buffers for Cb and Cr samples are each
1280 bytes deep. The incoming video data stream is separated into Y, Cb, and
Cr data streams, scaled (if selected) and the Y, Cb, and Cr buffers are filled.
Each of the three buffers has a memory-mapped location associated with it;
YSRC, CBSRC, and CRSRC. The YSRC, CBSRC, and CRSRC locations are
read only and are used by DMAs to access video data samples stored in the
FIFOs. Reads must always be 64 bits.
(three buffers). One section is 2560 bytes deep and is dedicated for storage
of Y data samples. The other two sections are dedicated for storage of Cb and
Cr data samples, respectively. The buffers for Cb and Cr samples are each
1280 bytes deep. The incoming video data stream is separated into Y, Cb, and
Cr data streams, scaled (if selected) and the Y, Cb, and Cr buffers are filled.
Each of the three buffers has a memory-mapped location associated with it;
YSRC, CBSRC, and CRSRC. The YSRC, CBSRC, and CRSRC locations are
read only and are used by DMAs to access video data samples stored in the
FIFOs. Reads must always be 64 bits.
If video capture is enabled, pixels in the capture window are captured in the
Y, Cb, and Cr buffers. The video capture module uses the YEVT, CbEVT, and
CrEVT events to notify the DMA controller to copy data from the capture buff-
ers to the DSP memory. The number of pixels required to generate the events
is set by the VCTHRLDn bits in VCxTHRLD (the VCTHRLDn value must be an
even number for Y/C mode). The capture module generates the events after
VCTHRLDn new pixels have been received. On every YEVT, the DMA should
move data from the Y buffer to DSP memory using the YSRC register as the
source address. On every CbEVT, the DMA should move data from the Cb
buffer to DSP memory using the CBSRC register as the source address. On
every CrEVT, the DMA should move data from the Cr buffer to DSP memory
using the CRSRC register as the source address. Note that transfer size from
the Cb and Cr buffers is half of the transfer size from the Y buffer since for every
four Y samples, there are two Cb and two Cr samples.
Y, Cb, and Cr buffers. The video capture module uses the YEVT, CbEVT, and
CrEVT events to notify the DMA controller to copy data from the capture buff-
ers to the DSP memory. The number of pixels required to generate the events
is set by the VCTHRLDn bits in VCxTHRLD (the VCTHRLDn value must be an
even number for Y/C mode). The capture module generates the events after
VCTHRLDn new pixels have been received. On every YEVT, the DMA should
move data from the Y buffer to DSP memory using the YSRC register as the
source address. On every CbEVT, the DMA should move data from the Cb
buffer to DSP memory using the CBSRC register as the source address. On
every CrEVT, the DMA should move data from the Cr buffer to DSP memory
using the CRSRC register as the source address. Note that transfer size from
the Cb and Cr buffers is half of the transfer size from the Y buffer since for every
four Y samples, there are two Cb and two Cr samples.
The three DMA events are generated simultaneously when VCTHRLDn is
reached. Each event is reenabled when the first read of the respective FIFO
by the requested DMA begins.
reached. Each event is reenabled when the first read of the respective FIFO
by the requested DMA begins.