Texas Instruments TMS320C64x DSP Benutzerhandbuch
BT.656 and Y/C Mode Field and Frame Operation
3-25
Video Capture Port
SPRU629
The field detect method uses HYSNC and VSYNC based field detect logic.
This is used for BT.656 or Y/C systems that provide only HSYNC and VSYNC.
The field detect logic samples the state of the HSYNC input on the VSYNC
active edge. If HSYNC is active on the active VSYNC edge, then field 1 is
detected; if HSYNC is inactive on the active VSYNC edge, then field 2 is detec-
ted. Because of slight timing variations, the VSYNC transition may not coincide
exactly with the HSYNC transition. The detection logic should implement a
This is used for BT.656 or Y/C systems that provide only HSYNC and VSYNC.
The field detect logic samples the state of the HSYNC input on the VSYNC
active edge. If HSYNC is active on the active VSYNC edge, then field 1 is
detected; if HSYNC is inactive on the active VSYNC edge, then field 2 is detec-
ted. Because of slight timing variations, the VSYNC transition may not coincide
exactly with the HSYNC transition. The detection logic should implement a
±
64 clock detection window around HSYNC. If both HSYNC and VSYNC
leading edges occur within 64 cycles of each other, then field 1 is detected;
otherwise, field 2 is assumed. This is shown in Figure 3–11 for active-low sync
signals.
otherwise, field 2 is assumed. This is shown in Figure 3–11 for active-low sync
signals.
Figure 3–11.Field 1 Detection Timing
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
HSYNC#
(VCTL1)
VCLKIN
VSYNC#
(VCTL2)
64 Clocks
64 Clocks
3.4.5
Short and Long Field Detect
The short and long field detect logic is used to notify the DSP when a captured
field shorter or longer than expected. Detection is enabled by the SFDE and
LFDE bits in VCxCTL. The SFD and LFD bits in VPIS indicate when a short
or long field occurred and trigger an interrupt to the DSP if enabled.
field shorter or longer than expected. Detection is enabled by the SFDE and
LFDE bits in VCxCTL. The SFD and LFD bits in VPIS indicate when a short
or long field occurred and trigger an interrupt to the DSP if enabled.
If a vertical blanking period is detected before the end of the capture field, a
short field is detected . If EAV is used for vertical sync (EXC = 0), then a short
field is detected when an EAV with V = 1 occurs on or before
VCOUNT = VCYSTOPn. If the VCTL2 input is used for vertical sync
(EXC = 1), then a short field is detected if a VCTL2 active edge occurs before
VCOUNT = VCYSTOPn.
short field is detected . If EAV is used for vertical sync (EXC = 0), then a short
field is detected when an EAV with V = 1 occurs on or before
VCOUNT = VCYSTOPn. If the VCTL2 input is used for vertical sync
(EXC = 1), then a short field is detected if a VCTL2 active edge occurs before
VCOUNT = VCYSTOPn.
If a vertical blanking period occurs more than 1 line past the end of the capture
field, a long field is detected. A long field is detected when
VCOUNT = VCYSTOPn + 1. (A long field is only detected when the VRST bit
in VCxCTL is cleared to 0; when VRST = 1, a long field is always detected.)
Long field detection cannot be used if the capture window is a vertical subset
of the field that crops lines at the bottom. Such a window would always result
in a long field detection. If VCTL2 is used for vertical sync, then the VCTL2 sig-
nal must represent VBLNK (vertical blank) for proper long field detect. If
field, a long field is detected. A long field is detected when
VCOUNT = VCYSTOPn + 1. (A long field is only detected when the VRST bit
in VCxCTL is cleared to 0; when VRST = 1, a long field is always detected.)
Long field detection cannot be used if the capture window is a vertical subset
of the field that crops lines at the bottom. Such a window would always result
in a long field detection. If VCTL2 is used for vertical sync, then the VCTL2 sig-
nal must represent VBLNK (vertical blank) for proper long field detect. If