Texas Instruments TMS320C64x DSP Benutzerhandbuch

3-33

VCxCTL Bit

0

0

x

x

Noncontinuous frame capture. FRMC is set after data block capture
and causes CCMPx to be set. Capture will halt upon completion of the
next frame unless the FRMC bit is cleared. (DSP has the entire next
frame time to clear FRMC.)

0

1

x

x

Single frame capture. FRMC is set after data block capture and causes
CCMPx to be set. Capture is halted until the FRMC bit is cleared.

1

0

x

x

Continuous frame capture. FRMC is set after data block capture and
causes CCMPx to be set (CCMPx interrupt can be disabled). The port
will continue capturing frames regardless of the state of FRMC.

1

1

x

x

Reserved

The CON bit controls the capture of multiple frames. When CON = 1, continuous
capture is enabled, the video port captures incoming frames (assuming the
VCEN bit is set) without the need for DSP interaction. It relies on a DMA
structure with circular buffering capability to service the capture FIFO. When
CON  =  0, continuous capture is disabled, the video port sets the frame capture
complete bit (FRMC) in VCxSTAT upon the capture of each frame. Once the
capture complete bit is set, at most, one more frame can be received before
capture operation is halted (as determined by the FRAME bit state). This
prevents subsequent data from overwriting previous frames until the DSP has
a chance to update DMA pointers or process those frames.

Captured data is always packed into 64-bits before being written into the
capture FIFO(s). The packing and byte ordering is dependant upon the
capture data size and the device endian mode. For little-endian operation
(default), data is packed into the FIFO from right to left; for big-endian opera-
tion, data is packed from left to right.