Texas Instruments TMS320C645x DSP Benutzerhandbuch
www.ti.com
5.22 Receive Unicast Enable Set Register (RXUNICASTSET)
EMAC Port Registers
Table 49. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field
Descriptions (continued)
Bit
Field
Value
Description
2-0
RXMULTCH
0-3h
Receive multicast channel select
0
Select channel 0 to receive multicast frames
1h
Select channel 1 to receive multicast frames
2h
Select channel 2 to receive promiscuous frames
3h
Select channel 3 to receive multicast frames
4h
Select channel 4 to receive multicast frames
5h
Select channel 5 to receive multicast frames
6h
Select channel 6 to receive multicast frames
7h
Select channel 7 to receive multicast frames
The receive unicast enable set register (RXUNICASTSET) is shown in
and described in
.
Figure 50. Receive Unicast Enable Set Register (RXUNICASTSET)
31
16
Reserved
R-0
15
8
7
6
5
4
3
2
1
0
Reserved
RXCH7EN
RXCH6EN
RXCH5EN
RXCH4EN
RXCH3EN
RXCH2EN
RXCH1EN
RXCH0EN
R-0
R/WS-0
R/WS-0
R/WS-0
R/WS-0
R/WS-0
R/WS-0
R/WS-0
R/WS-0
LEGEND: R = Read only; R/W = Read/Write; R/WS = Read/Write 1 to set; -n = value after reset
Table 50. Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7
RXCH7EN
Receive channel 7 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May
be read.
be read.
6
RXCH6EN
Receive channel 6 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May
be read.
be read.
5
RXCH5EN
Receive channel 5 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May
be read.
be read.
4
RXCH4EN
Receive channel 4 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May
be read.
be read.
3
RXCH3EN
Receive channel 3 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May
be read.
be read.
2
RXCH2EN
Receive channel 2 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May
be read.
be read.
1
RXCH1EN
Receive channel 1 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May
be read.
be read.
0
RXCH0EN
Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May
be read.
be read.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
106
SPRU975B – August 2006