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5.23 Receive Unicast Clear Register (RXUNICASTCLEAR)
EMAC Port Registers
The receive unicast clear register (RXUNICASTCLEAR) is shown in
and described in
.
Figure 51. Receive Unicast Clear Register (RXUNICASTCLEAR)
31
16
Reserved
R-0
15
8
7
6
5
4
3
2
1
0
Reserved
RXCH7EN
RXCH6EN
RXCH5EN
RXCH4EN
RXCH3EN
RXCH2EN
RXCH1EN
RXCH0EN
R-0
R/WC-0
R/WC-0
R/WC-0
R/WC-0
R/WC-0
R/WC-0
R/WC-0
R/WC-0
LEGEND: R = Read only; R/W = Read/Write; R/WC = Read/Write 1 to clear; -n = value after reset
Table 51. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7
RXCH7EN
Receive channel 7 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
6
RXCH6EN
Receive channel 6 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
5
RXCH5EN
Receive channel 5 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
4
RXCH4EN
Receive channel 4 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
3
RXCH3EN
Receive channel 3 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
2
RXCH2EN
Receive channel 2 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
1
RXCH1EN
Receive channel 1 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
0
RXCH0EN
Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.
SPRU975B – August 2006
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
107