Texas Instruments TMS320C6747 DSP Benutzerhandbuch
3.6
HC Interrupt Disable Register (HCINTERRUPTDISABLE)
Registers
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The HC interrupt disable register (HCINTERRUPTDISABLE) is used to clear bits in the HC interrupt
enable register (HCINTERRUPTENABLE). HCINTERRUPTDISABLE is shown in
enable register (HCINTERRUPTENABLE). HCINTERRUPTDISABLE is shown in
and described
in
Figure 7. HC Interrupt Disable Register (HCINTERRUPTDISABLE)
31
30
29
16
MIE
OC
Reserved
R/W-0
R-0
R-0
15
7
6
5
4
3
2
1
0
Reserved
RHSC
FNO
UE
RD
SF
WDH
SO
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. HC Interrupt Disable Register (HCINTERRUPTDISABLE) Field Descriptions
Bit
Field
Value
Description
31
MIE
Master interrupt enable. Read always returns 0.
0
No effect.
1
Clears the MIE bit in the HC interrupt enable register (HCINTERRUPTENABLE).
30
OC
0-1
Ownership change.
29-7
Reserved
0
Reserved
6
RHSC
Root hub status change. Read always returns 0.
0
No effect.
1
Clears the RHSC bit in the HC interrupt enable register (HCINTERRUPTENABLE).
5
FNO
Frame number overflow. Read always returns 0.
0
No effect.
1
Clears the FNO bit in the HC interrupt enable register (HCINTERRUPTENABLE).
4
UE
Unrecoverable error. Read always returns 0.
0
No effect.
1
Clears the UE bit in the HC interrupt enable register (HCINTERRUPTENABLE).
3
RD
Resume detected. Read always returns 0.
0
No effect.
1
Clears the RD bit in the HC interrupt enable register (HCINTERRUPTENABLE).
2
SF
Start of frame. Read always returns 0.
0
No effect.
1
Clears the SF bit in the HC interrupt enable register (HCINTERRUPTENABLE).
1
WDH
Write done head. Read always returns 0.
0
No effect.
1
Clears the WDH bit in the HC interrupt enable register (HCINTERRUPTENABLE).
0
SO
Scheduling overrun. Read always returns 0.
0
No effect.
1
Clears the SO bit in the HC interrupt enable register (HCINTERRUPTENABLE).
Universal Serial Bus OHCI Host Controller
18
SPRUFM8 – September 2008