Texas Instruments TMS320C6747 DSP Benutzerhandbuch
3.9
HC Head Control Register (HCCONTROLHEADED)
Registers
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The HC head control register (HCCONTROLHEADED) defines the physical address of the head endpoint
descriptor (ED) on the control ED list. HCCONTROLHEADED is shown in
descriptor (ED) on the control ED list. HCCONTROLHEADED is shown in
and described in
.
Figure 10. HC Head Control Register (HCCONTROLHEADED)
31
16
CHED
R/W-0
15
4
3
0
CHED
Reserved
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. HC Head Control Register (HCCONTROLHEADED) Field Descriptions
Bit
Field
Value
Description
31-4
CHED
0-FFF FFFFh Physical address of the head ED on the control ED list. This field represents bits 31-4 of the
physical address of the head ED on the control ED list. EDs are assumed to begin on a 16-byte
aligned address, so bits 3-0 of this pointer are assumed to be 0. For the restrictions on physical
addresses, see
aligned address, so bits 3-0 of this pointer are assumed to be 0. For the restrictions on physical
addresses, see
.
3-0
Reserved
0
Reserved
20
Universal Serial Bus OHCI Host Controller
SPRUFM8 – September 2008