Texas Instruments TMS320C6747 DSP Benutzerhandbuch
3.22 HC Port 1 Status and Control Register (HCRHPORTSTATUS1)
Registers
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The HC port 1 status and control register (HCRHPORTSTATUS1) reports and controls the state of USB
host port 1. HCRHPORTSTATUS1 is shown in
host port 1. HCRHPORTSTATUS1 is shown in
and described in
.
Figure 23. HC Port 1 Status and Control Register (HCRHPORTSTATUS1)
31
21
20
19
18
17
16
Reserved
PRSC
OCIC
PSSC
PESC
CSC
R-0
R/W1C-0
R/W-0
R/W1C-0 R/W1C-0 R/W1C-0
15
10
9
8
Reserved
LSDA/CPP
PPS/SPP
R-0
R/W-0
R/W-1
7
5
4
3
2
1
0
Reserved
PRS/SPR
POCI/CSS
PSS/SPS
PES/SPE
CCS/CPE
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 23. HC Port 1 Status and Control Register (HCRHPORTSTATUS1) Field Descriptions
Bit
Field
Value
Description
31-21
Reserved
0
Reserved
20
PRSC
Port 1 reset status change. A write of 1 clears this bit; a write of 0 has no effect.
0
Port 1 port reset status bit has not changed.
1
Port 1 port reset status bit has changed.
19
OCIC
0
Port 1 overcurrent indicator change. Because the device does not provide inputs for signaling
external overcurrent indication to the USB host controller, this bit is always 0. Overcurrent
monitoring, if required, must be handled through some other mechanism. This bit has no
relationship to the OTG controller register bits that relate to VBUS.
external overcurrent indication to the USB host controller, this bit is always 0. Overcurrent
monitoring, if required, must be handled through some other mechanism. This bit has no
relationship to the OTG controller register bits that relate to VBUS.
18
PSSC
Port 1 suspend status change. A write of 1 clears this bit; a write of 0 has no effect.
0
Port 1 port suspend status has not changed.
1
Port 1 port suspend status has changed. Suspend status is considered to have changed only after
the resume pulse, low-speed EOP, and 3-ms synchronization delays have been completed.
the resume pulse, low-speed EOP, and 3-ms synchronization delays have been completed.
17
PESC
Port 1 enable status change. A write of 1 clears this bit; a write of 0 has no effect.
0
Port 1 port enable status has not changed.
1
Port 1 port enable status has changed.
16
CSC
Port 1 connect status change. If the DR[1] bit in the HC root hub B register (HCRHDESCRIPTORB)
is set to 1 to indicate a nonremovable USB device on port 1, this bit is set only after a root hub
reset to inform the system that the device is attached. A write of 1 clears this bit; a write of 0 has no
effect.
is set to 1 to indicate a nonremovable USB device on port 1, this bit is set only after a root hub
reset to inform the system that the device is attached. A write of 1 clears this bit; a write of 0 has no
effect.
0
Port 1 current connect status has not changed.
1
Port 1 current connect status has changed due to a connect or disconnect event. If current connect
status is 0 when a set port reset, set port enable, or set port suspend write occurs, then this bit is
set.
status is 0 when a set port reset, set port enable, or set port suspend write occurs, then this bit is
set.
15-10
Reserved
0
Reserved
9
LSDA/CPP
Port 1 low-speed device attached/clear port power. This bit is valid only when port 1 current
connect status is 1. The host controller driver can write a 1 to this bit to clear the port 1 port power
status bit; a write of 0 has no effect. The USB host controller does not control external port power
using OHCI mechanisms, so, if required, USB host port power must be controlled through other
means. This bit has no relationship to the OTG controller register bits that relate to VBUS. System
software can update this register to simplify host controller driver and/or OTG driver coding.
connect status is 1. The host controller driver can write a 1 to this bit to clear the port 1 port power
status bit; a write of 0 has no effect. The USB host controller does not control external port power
using OHCI mechanisms, so, if required, USB host port power must be controlled through other
means. This bit has no relationship to the OTG controller register bits that relate to VBUS. System
software can update this register to simplify host controller driver and/or OTG driver coding.
0
Full-speed device is attached to port 1.
1
Low-speed device is attached to port 1.
30
Universal Serial Bus OHCI Host Controller
SPRUFM8 – September 2008