Texas Instruments TMS320TCI648x Benutzerhandbuch
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5.8
Block n Enable Status Register (BLKn_EN_STAT)
SRIO Registers
There are nine of these registers, one for each of nine logical blocks in the peripheral. The registers and
the blocks they support are listed in
the blocks they support are listed in
. The general form for a block n enable status register
(BLKn_EN_STAT) is shown in
and described in
. For additional programming
information, see
Table 48. Block n Enable Status Registers and the Associated Blocks
Register
Address Offset
Associated Block
BLK0_EN_STAT
003Ch
Logical block 0: the set of memory-mapped control registers for the SRIO
peripheral
peripheral
BLK1_EN_STAT
0044h
Logical block 1: the Load/Store module (the four LSUs and supporting logic)
BLK2_EN_STAT
004Ch
Logical block 2: the memory access unit (MAU)
BLK3_EN_STAT
0054h
Logical block 3: the message transmit unit (TXU)
BLK4_EN_STAT
005Ch
Logical block 4: the message receive unit (RXU).
BLK5_EN_STAT
0064h
Logical block 5: SRIO port 0
BLK6_EN_STAT
006Ch
Logical block 6: SRIO port 1.
BLK7_EN_STAT
0074h
Logical block 7: SRIO port 2.
BLK8_EN_STAT
007Ch
Logical block 8: SRIO port 3.
Figure 69. Block n Enable Status Register (BLKn_EN)
31
1
0
Reserved
EN_STAT
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 49. Block n Enable Status Register (BLKn_EN_STAT) Field Descriptions
Bit
Field
Value
Description
31-1
Reserved
0
These read-only bits return 0s when read.
0
EN_STAT
Block n enable status
0
Logical block n is reset with its clock off.
1
Logical block n is enabled with its clock running.
Serial RapidIO (SRIO)
120
SPRUE13A – September 2006