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5.9
RapidIO DEVICEID1 Register (DEVICEID_REG1)
SRIO Registers
The RapidIO DEVICEID1 register (DEVICEID_REG1) is shown in
and described in
Figure 70. RapidIO DEVICEID1 Register (DEVICEID_REG1) (Offset 0080h)
31
24 23
16
Reserved
8BNODEID
R-00h
R/W-FFh
15
0
16BNODEID
R/W-FFFFh
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 50. RapidIO DEVICEID1 Register (DEVICEID_REG1) Field Descriptions
Bit
Field
Value
Description
31–24
Reserved
0
Reserved
23–16
8BNODEID
00h–FFh
This value is equal to the value of the RapidIO Base Device ID CSR. The CPU must
read the CSR value and set this register, so that outgoing packets contain the correct
SOURCEID value
read the CSR value and set this register, so that outgoing packets contain the correct
SOURCEID value
15–0
16BNODEID
0000h–FFFFh
This value is equal to the value of the RapidIO Base Device ID CSR. The CPU must
read the CSR value and set this register, so that outgoing packets contain the correct
SOURCEID value
read the CSR value and set this register, so that outgoing packets contain the correct
SOURCEID value
SPRUE13A – September 2006
Serial RapidIO (SRIO)
121