Intel 820E Benutzerhandbuch

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Intel
®
 820E Chipset 
 
 
 
 
R
 
110  
Design 
Guide 
2.22.2.3. 
4-Layer Board Design 
Top-Layer Routing 
Sensitive analog signals are routed completely on the top layer without the use of vias. This allows tight 
control of signal integrity and removes any impedance inconsistencies due to layer changes. 
Ground Plane 
A layout split (100 mils) of the ground plane under the magnetics module between the primary and 
secondary side of the module is recommended.  
Power Plane 
Physically separate digital and analog power planes must be provided to prevent digital switching noise 
from being coupled into the analog power supply plane’s VDD_A. Analog power may be a metal fill 
“island,” separated from digital power, and better filtered than digital power.  
Bottom Layer Routing 
The digital high-speed signals, which include all LAN interconnect interface signals, are routed on the 
bottom layer.  
Common Physical Layout Issues 
The most common physical layer design and layout mistakes in LAN-on-motherboard designs are as 
follows: 
1.  Unequal length of the two traces within a differential pair. Inequalities create common-mode 
noise which will distort the transmit or receive waveforms. 
2.  Lack of symmetry between the two traces within a differential pair. (For each component and/or 
via that one trace encounters, the other trace must encounter the same component or a via at the 
same distance from the PLC.) Asymmetry can create common-mode noise and distort the 
waveforms. 
3.  Excessive distance between the PLC and the magnetics or between the magnetics and the RJ-
45/11 connector. Beyond a total distance of about 4 inches, it can become extremely difficult to 
design a spec-compliant LAN product. If they are long, traces on FR4 (fiberglass epoxy substrate) 
will attenuate the analog signals. Also, longer traces will increase the impedance mismatch (see 
mistake 9). The magnetics should be as close to the connector as possible (<= 1 inch). 
4.  Routing any other trace parallel to and close to one of the differential traces. Crosstalk on the 
receive channel will degrade the long-cable BER. Crosstalk on the transmit channel can cause 
excessive emissions—resulting in FCC test failure—and can result in a low transmission BER on 
long cables. Other signals should be kept at least 0.3 inch from the differential traces. 
5.  Routing the transmit differential traces next to the receive differential traces. The transmit 
trace closest to a receive trace will induce more crosstalk on the closest receive trace, and it can 
greatly degrade the receiver’s BER over long cables. After exiting the PLC, the transmit traces