Intel 820E Benutzerhandbuch
Intel
®
820E Chipset
R
142
Design
Guide
3.2.1.
Initial Timing Analysis
Perform an initial timing analysis of the system using the following two equations, which are the basis for
timing analysis. To complete the initial timing analysis, values for clock skew and clock jitter are needed,
along with the component specifications. These equations contain a multi-bit adjustment factor, M
timing analysis. To complete the initial timing analysis, values for clock skew and clock jitter are needed,
along with the component specifications. These equations contain a multi-bit adjustment factor, M
ADJ
, to
account for multi-bit switching effects (e.g., SSO push-out or pull-in) that often are hard to simulate.
These equations do not take into consideration all signal integrity factors that affect timing. Additional
timing margin should be budgeted to allow for these sources of noise.
These equations do not take into consideration all signal integrity factors that affect timing. Additional
timing margin should be budgeted to allow for these sources of noise.
Equation 4. Setup Time
T
CO_MAX
+ T
SU_MIN
+ CLK
SKEW
+ CLK
JITTER
+ T
FLT_MAX
+ M
ADJ
≤
Clock period
Equation 5. Hold Time
T
CO_MIN
+ T
FLT_MIN
–
M
ADJ
≥
T
HOLD
+ CLK
SKEW
Symbols used in these two equations:
T
CO_MAX
Max. clock-to-output specification (see Note)
T
SU_MIN
Min. required time specified to setup before the clock (see Note)
CLK
JITTER
Max. clock edge-to-edge variation.
CLK
SKEW
Max. variation between components receiving the same clock edge
T
FLT_MAX
Max. flight time, as defined in Section 3.1
T
FLT_MIN
Min. flight time, as defined in Section 3.1
M
ADJ
Multi-bit adjustment factor to account for SSO push-out or pull-in
T
CO_MIN
Min. clock-to-output specification (see Note)
T
HOLD
Min. specified input hold time
Note: The clock-to-output (T
CO
) and setup-to-clock (T
SU
) timings are both measured from the signal’s last
crossing of V
REF
, with the requirement that the signal does not violate the ringback or edge rate limits.
See the respective processor’s datasheet and the Pentium
®
III Processor Developer’s Manual for more
details.
Solving these equations for T
FLT
yields the following equations:
Equation 6. Maximum Flight Time
T
FLT_MAX
≤
Clock period – T
CO_MAX
– T
SU_MIN
– CLK
SKEW
– CLK
JITTER
– M
ADJ
Equation 7. Minimum Flight Time
T
FLT_MIN
≥
T
HOLD
+ CLK
SKEW
– T
CO_MIN
+ M
ADJ
Multiple cases must be considered. Note that while the same trace connects two components, component
A and component B, the minimum and maximum flight time requirements for component A driving
component B as well as component B driving component A must be met. The cases to be considered are:
A and component B, the minimum and maximum flight time requirements for component A driving
component B as well as component B driving component A must be met. The cases to be considered are:
•
Processor driving processor
•
Processor driving chipset
•
Chipset driving processor