Intel 253668-032US Benutzerhandbuch
Vol. 3 6-9
INTERRUPT AND EXCEPTION HANDLING
It is possible to issue a maskable hardware interrupt (through the INTR pin) to vector
2 to invoke the NMI interrupt handler; however, this interrupt will not truly be an NMI
interrupt. A true NMI interrupt that activates the processor’s NMI-handling hardware
can only be delivered through one of the mechanisms listed above.
2 to invoke the NMI interrupt handler; however, this interrupt will not truly be an NMI
interrupt. A true NMI interrupt that activates the processor’s NMI-handling hardware
can only be delivered through one of the mechanisms listed above.
6.7.1
Handling Multiple NMIs
While an NMI interrupt handler is executing, the processor disables additional calls to
the NMI handler until the next IRET instruction is executed. This blocking of subse-
quent NMIs prevents stacking up calls to the NMI handler. It is recommended that the
NMI interrupt handler be accessed through an interrupt gate to disable maskable
hardware interrupts (see Section 6.8.1, “Masking Maskable Hardware Interrupts”). If
the NMI handler is a virtual-8086 task with an IOPL of less than 3, an IRET instruction
issued from the handler generates a general-protection exception (see Section
17.2.7, “Sensitive Instructions”). In this case, the NMI is unmasked before the
general-protection exception handler is invoked.
the NMI handler until the next IRET instruction is executed. This blocking of subse-
quent NMIs prevents stacking up calls to the NMI handler. It is recommended that the
NMI interrupt handler be accessed through an interrupt gate to disable maskable
hardware interrupts (see Section 6.8.1, “Masking Maskable Hardware Interrupts”). If
the NMI handler is a virtual-8086 task with an IOPL of less than 3, an IRET instruction
issued from the handler generates a general-protection exception (see Section
17.2.7, “Sensitive Instructions”). In this case, the NMI is unmasked before the
general-protection exception handler is invoked.
6.8
ENABLING AND DISABLING INTERRUPTS
The processor inhibits the generation of some interrupts, depending on the state of
the processor and of the IF and RF flags in the EFLAGS register, as described in the
following sections.
the processor and of the IF and RF flags in the EFLAGS register, as described in the
following sections.
6.8.1
Masking Maskable Hardware Interrupts
The IF flag can disable the servicing of maskable hardware interrupts received on the
processor’s INTR pin or through the local APIC (see Section 6.3.2, “Maskable Hard-
ware Interrupts”). When the IF flag is clear, the processor inhibits interrupts deliv-
ered to the INTR pin or through the local APIC from generating an internal interrupt
request; when the IF flag is set, interrupts delivered to the INTR or through the local
APIC pin are processed as normal external interrupts.
The IF flag does not affect non-maskable interrupts (NMIs) delivered to the NMI pin
or delivery mode NMI messages delivered through the local APIC, nor does it affect
processor generated exceptions. As with the other flags in the EFLAGS register, the
processor clears the IF flag in response to a hardware reset.
The fact that the group of maskable hardware interrupts includes the reserved inter-
rupt and exception vectors 0 through 32 can potentially cause confusion. Architectur-
ally, when the IF flag is set, an interrupt for any of the vectors from 0 through 32 can
be delivered to the processor through the INTR pin and any of the vectors from 16
through 32 can be delivered through the local APIC. The processor will then generate
an interrupt and call the interrupt or exception handler pointed to by the vector
number. So for example, it is possible to invoke the page-fault handler through the
INTR pin (by means of vector 14); however, this is not a true page-fault exception. It
processor’s INTR pin or through the local APIC (see Section 6.3.2, “Maskable Hard-
ware Interrupts”). When the IF flag is clear, the processor inhibits interrupts deliv-
ered to the INTR pin or through the local APIC from generating an internal interrupt
request; when the IF flag is set, interrupts delivered to the INTR or through the local
APIC pin are processed as normal external interrupts.
The IF flag does not affect non-maskable interrupts (NMIs) delivered to the NMI pin
or delivery mode NMI messages delivered through the local APIC, nor does it affect
processor generated exceptions. As with the other flags in the EFLAGS register, the
processor clears the IF flag in response to a hardware reset.
The fact that the group of maskable hardware interrupts includes the reserved inter-
rupt and exception vectors 0 through 32 can potentially cause confusion. Architectur-
ally, when the IF flag is set, an interrupt for any of the vectors from 0 through 32 can
be delivered to the processor through the INTR pin and any of the vectors from 16
through 32 can be delivered through the local APIC. The processor will then generate
an interrupt and call the interrupt or exception handler pointed to by the vector
number. So for example, it is possible to invoke the page-fault handler through the
INTR pin (by means of vector 14); however, this is not a true page-fault exception. It